[llvm] [RISCV] Teach expandRV32ZdinxStore to handle memoperand not being present. (PR #113981)

[Gergely Futo via llvm-commits]

futog wrote:

Hi Craig,

the issue is still there with the following MIR:
`PseudoRV32ZdinxSD killed renamable $x10_x11, killed renamable $x12, 8 :: (store (s64) into %ir.arrayidx13, !tbaa !6), (store (s64) into %ir.arrayidx20, !tbaa !6)
`
Assertion: `assert(MBBI->hasOneMemOperand() && "Expected mem operand");`

Regards,
Gergely

https://github.com/llvm/llvm-project/pull/113981