[llvm] 0ef39a8 - MachineCSE: Remove check for subreg on a def operand (#124095)

[via llvm-commits]

Author: Matt Arsenault
Date: 2025-01-24T09:35:30+07:00
New Revision: 0ef39a882bb342982929d2c856d7865de147a3c7

URL: https://github.com/llvm/llvm-project/commit/0ef39a882bb342982929d2c856d7865de147a3c7
DIFF: https://github.com/llvm/llvm-project/commit/0ef39a882bb342982929d2c856d7865de147a3c7.diff

LOG: MachineCSE: Remove check for subreg on a def operand (#124095)

There are no subregister defs in SSA.

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineCSE.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 728fd2f5f7cd4f..bea0eaf206f5ee 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -187,8 +187,6 @@ bool MachineCSEImpl::PerformTrivialCopyPropagation(MachineInstr *MI,
     Register SrcReg = DefMI->getOperand(1).getReg();
     if (!SrcReg.isVirtual())
       continue;
-    if (DefMI->getOperand(0).getSubReg())
-      continue;
     // FIXME: We should trivially coalesce subregister copies to expose CSE
     // opportunities on instructions with truncated operands (see
     // cse-add-with-overflow.ll). This can be done here as follows: