[llvm] [RISCV][NFC] Remove Redundant Inline Asm Logic (PR #124202)

[Sam Elliott via llvm-commits]

https://github.com/lenary created https://github.com/llvm/llvm-project/pull/124202

This was left over from 408659c5b5c7d745042ae71db344d1ed10601512.

>From b04091b833ea9125efcd8b926731aa37d42a1dba Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Thu, 23 Jan 2025 14:39:27 -0800
Subject: [PATCH] [RISCV][NFC] Remove Redundant Inline Asm Logic

This was left over from 408659c5b5c7d745042ae71db344d1ed10601512.
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 --
 1 file changed, 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f7efd5f437fbb1..a2c1a986d4034f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21133,8 +21133,6 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       }
       break;
     case 'R':
-      if (VT == MVT::f64 && !Subtarget.is64Bit() && Subtarget.hasStdExtZdinx())
-        return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
       return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
     default:
       break;