[llvm] [AMDGPU][True16][MC] true16 for minimummaximum/max/min/max3/min3 (PR #124184)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 1a8f49fdda5b14ccc894aacee653f19130df3a30 190473aa29e942f270ba32bb31ea2f34228130a1 --extensions cpp -- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 528e848288..26f6308d93 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7570,25 +7570,25 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
   }
   case AMDGPU::S_MINIMUM_F16:
   case AMDGPU::S_MAXIMUM_F16: {
-      const DebugLoc &DL = Inst.getDebugLoc();
-      Register NewDst;
-      if (ST.useRealTrue16Insts())
-        NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
-      else
-        NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
-      MachineInstr *NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
-                                   .addImm(0) // src0_modifiers
-                                   .add(Inst.getOperand(1))
-                                   .addImm(0) // src1_modifiers
-                                   .add(Inst.getOperand(2))
-                                   .addImm(0)  // clamp
-                                   .addImm(0)  // omod
-                                   .addImm(0); // opsel0
-      MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);
-      legalizeOperands(*NewInstr, MDT);
-      addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist);
-      Inst.eraseFromParent();
-      return;
+    const DebugLoc &DL = Inst.getDebugLoc();
+    Register NewDst;
+    if (ST.useRealTrue16Insts())
+      NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
+    else
+      NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+    MachineInstr *NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
+                                 .addImm(0) // src0_modifiers
+                                 .add(Inst.getOperand(1))
+                                 .addImm(0) // src1_modifiers
+                                 .add(Inst.getOperand(2))
+                                 .addImm(0)  // clamp
+                                 .addImm(0)  // omod
+                                 .addImm(0); // opsel0
+    MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);
+    legalizeOperands(*NewInstr, MDT);
+    addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist);
+    Inst.eraseFromParent();
+    return;
   }
   }
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/124184