[llvm] e19261f - [TableGen] Add a SmallPtrSet to track WriteRes that are referenced by some ReadAdvance. NFC (#124160)

[via llvm-commits]

Author: Craig Topper
Date: 2025-01-23T12:48:59-08:00
New Revision: e19261faf5c771bd7951b987abe8de698469e9f1

URL: https://github.com/llvm/llvm-project/commit/e19261faf5c771bd7951b987abe8de698469e9f1
DIFF: https://github.com/llvm/llvm-project/commit/e19261faf5c771bd7951b987abe8de698469e9f1.diff

LOG: [TableGen] Add a SmallPtrSet to track WriteRes that are referenced by some ReadAdvance. NFC (#124160)

Use this to remove a linear scan from CodeGenProcModel::hasReadOfWrite.

This reduces build time of RISCVGenSubtargetInfo.inc on by machine from
~6 seconds to ~3 seconds.

Added: 
    

Modified: 
    llvm/utils/TableGen/Common/CodeGenSchedule.cpp
    llvm/utils/TableGen/Common/CodeGenSchedule.h

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index 8919a278f352bf..e84b4fd77a6c1f 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -2129,13 +2129,15 @@ void CodeGenSchedModels::addWriteRes(const Record *ProcWriteResDef,
 void CodeGenSchedModels::addReadAdvance(const Record *ProcReadAdvanceDef,
                                         CodeGenProcModel &PM) {
   for (const Record *ValidWrite :
-       ProcReadAdvanceDef->getValueAsListOfDefs("ValidWrites"))
+       ProcReadAdvanceDef->getValueAsListOfDefs("ValidWrites")) {
     if (getSchedRWIdx(ValidWrite, /*IsRead=*/false) == 0)
       PrintFatalError(
           ProcReadAdvanceDef->getLoc(),
           "ReadAdvance referencing a ValidWrite that is not used by "
           "any instruction (" +
               ValidWrite->getName() + ")");
+    PM.ReadOfWriteSet.insert(ValidWrite);
+  }
 
   ConstRecVec &RADefs = PM.ReadAdvanceDefs;
   if (is_contained(RADefs, ProcReadAdvanceDef))
@@ -2173,12 +2175,7 @@ bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {
 }
 
 bool CodeGenProcModel::hasReadOfWrite(const Record *WriteDef) const {
-  for (auto &RADef : ReadAdvanceDefs) {
-    ConstRecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");
-    if (is_contained(ValidWrites, WriteDef))
-      return true;
-  }
-  return false;
+  return ReadOfWriteSet.count(WriteDef);
 }
 
 #ifndef NDEBUG

diff  --git a/llvm/utils/TableGen/Common/CodeGenSchedule.h b/llvm/utils/TableGen/Common/CodeGenSchedule.h
index 5d5aa44d882e59..0dce1fa308118e 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.h
@@ -19,6 +19,7 @@
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/SetTheory.h"
@@ -250,6 +251,9 @@ struct CodeGenProcModel {
   // Map from the ReadType field to the parent ReadAdvance record.
   DenseMap<const Record *, const Record *> ReadAdvanceMap;
 
+  // Set of WriteRes that are referenced by a ReadAdvance.
+  SmallPtrSet<const Record *, 8> ReadOfWriteSet;
+
   // Per-operand machine model resources associated with this processor.
   ConstRecVec ProcResourceDefs;