[llvm] [AArch64] Codegen for new SCVTF/UCVTF variants (FEAT_FPRCVT) (PR #123767)

[via llvm-commits]

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@@ -5511,6 +5511,15 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
     let Inst{31} = 1; // 64-bit FPR flag
     let Inst{23-22} = 0b00; // 32-bit FPR flag
   }
+
+  def : Pat<(f16 (any_fpround (f32 (op (i32 FPR32:$Rn))))),
+          (!cast<Instruction>(NAME # HSr) $Rn)>;
+  def : Pat<(f64 (op (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
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CarolineConcatto wrote:

Yes, you are correct Spencer.

It is not for you to change the pattern, was for you to add test in llvm-ir with the lane different from zero. So we can see that the pattern does not work.

Sorry @virginia-cangelosi for not being clear on what I meant.

https://github.com/llvm/llvm-project/pull/123767