[llvm] [TableGen] Make sure BitWidth is set even if all instructions are Pseudo or TargetOpcode (PR #124071)

[Farzon Lotfi via llvm-commits]

farzonl wrote:

> Do you need to include the GenMCCodeEmitter.inc file? Is there something else in it you need?

My understanding is `GenMCCodeEmitter.inc` is used to emit the appropriate binary machine code for the specified target. I was writing up `dx.op.unary`as a pseudo instruction.  Below is the transformation I was trying to get working with my experiment:


| LLVMIR |MIR  | DXIL |
| :------- | :--: | ----: |
%1 = call float @llvm.sin.f32(float %0)  | %1:_(s32) = G_FSIN %0 | %Sin = call float @dx.op.unary.f32(i32 13, float %0) |

>From your hesitation it seems I shouldn't be defining this as a pseudo instruction?

I think at a minimum `CodeEmitterGen::run` should not proceed with codegen if BitWidth is 0 after the loop on line 488
`for (const CodeGenInstruction *CGI : NumberedInstructions) {`. Something that alerts you that not all Instructions can be Pseudo or TargetOpcode. This was a non obvious breaking case and required a fair amount of debugging the llvm-tablegen cmake invokations for my target.

https://github.com/llvm/llvm-project/pull/124071