[llvm] Enable CPU0 backend (PR #124114)
Yutao Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 23 05:40:54 PST 2025
https://github.com/WangYutao1995 created https://github.com/llvm/llvm-project/pull/124114
None
>From 5509ffadb146500a01be8b858cfefad8b70b1870 Mon Sep 17 00:00:00 2001
From: Yutao Wang <yutao.wang at intel.com>
Date: Thu, 23 Jan 2025 05:38:26 -0800
Subject: [PATCH] Enable CPU0 backend
---
llvm/include/llvm/TargetParser/Triple.h | 4 ++++
llvm/lib/Target/Cpu0/CMakeLists.txt | 14 ++++++++++++++
llvm/lib/Target/Cpu0/Cpu0TargetMachine.cpp | 5 +++++
llvm/lib/Target/Cpu0/MCTargetDesc/CMakeLists.txt | 7 +++++++
.../Target/Cpu0/MCTargetDesc/Cpu0MCTargetDesc.cpp | 5 +++++
llvm/lib/Target/Cpu0/TargetInfo/CMakeLists.txt | 7 +++++++
llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.cpp | 14 ++++++++++++++
llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.h | 12 ++++++++++++
llvm/lib/TargetParser/Triple.cpp | 6 ++++++
9 files changed, 74 insertions(+)
create mode 100644 llvm/lib/Target/Cpu0/CMakeLists.txt
create mode 100644 llvm/lib/Target/Cpu0/Cpu0TargetMachine.cpp
create mode 100644 llvm/lib/Target/Cpu0/MCTargetDesc/CMakeLists.txt
create mode 100644 llvm/lib/Target/Cpu0/MCTargetDesc/Cpu0MCTargetDesc.cpp
create mode 100644 llvm/lib/Target/Cpu0/TargetInfo/CMakeLists.txt
create mode 100644 llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.cpp
create mode 100644 llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.h
diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index 8097300c6e630c..b090aa1a69bacf 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -62,6 +62,7 @@ class Triple {
loongarch64, // LoongArch (64-bit): loongarch64
m68k, // M68k: Motorola 680x0 family
mips, // MIPS: mips, mipsallegrex, mipsr6
+ cpu0, // CPU0
mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
@@ -986,6 +987,9 @@ class Triple {
return isMIPS32() || isMIPS64();
}
+ /// Tests whether the target is CPU0
+ bool isCPU0() const { return getArch() == Triple::cpu0; }
+
/// Tests whether the target is PowerPC (32- or 64-bit LE or BE).
bool isPPC() const {
return getArch() == Triple::ppc || getArch() == Triple::ppc64 ||
diff --git a/llvm/lib/Target/Cpu0/CMakeLists.txt b/llvm/lib/Target/Cpu0/CMakeLists.txt
new file mode 100644
index 00000000000000..6919b1d4cf2b1a
--- /dev/null
+++ b/llvm/lib/Target/Cpu0/CMakeLists.txt
@@ -0,0 +1,14 @@
+add_llvm_component_group(Cpu0)
+
+add_llvm_target(Cpu0CodeGen
+ Cpu0TargetMachine.cpp
+
+ LINK_COMPONENTS
+ MC
+ Cpu0Info
+ Cpu0Desc
+ Support
+ )
+
+add_subdirectory(TargetInfo)
+add_subdirectory(MCTargetDesc)
\ No newline at end of file
diff --git a/llvm/lib/Target/Cpu0/Cpu0TargetMachine.cpp b/llvm/lib/Target/Cpu0/Cpu0TargetMachine.cpp
new file mode 100644
index 00000000000000..2ad9d34554a6cd
--- /dev/null
+++ b/llvm/lib/Target/Cpu0/Cpu0TargetMachine.cpp
@@ -0,0 +1,5 @@
+#include "llvm/MC/TargetRegistry.h"
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCpu0Target() {
+
+}
diff --git a/llvm/lib/Target/Cpu0/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Cpu0/MCTargetDesc/CMakeLists.txt
new file mode 100644
index 00000000000000..440fb4631fedbc
--- /dev/null
+++ b/llvm/lib/Target/Cpu0/MCTargetDesc/CMakeLists.txt
@@ -0,0 +1,7 @@
+add_llvm_component_library(LLVMCpu0Desc
+ Cpu0MCTargetDesc.cpp
+
+ LINK_COMPONENTS
+ MC
+ Support
+ )
\ No newline at end of file
diff --git a/llvm/lib/Target/Cpu0/MCTargetDesc/Cpu0MCTargetDesc.cpp b/llvm/lib/Target/Cpu0/MCTargetDesc/Cpu0MCTargetDesc.cpp
new file mode 100644
index 00000000000000..260c99be75c219
--- /dev/null
+++ b/llvm/lib/Target/Cpu0/MCTargetDesc/Cpu0MCTargetDesc.cpp
@@ -0,0 +1,5 @@
+#include "llvm/MC/TargetRegistry.h"
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCpu0TargetMC() {
+
+}
diff --git a/llvm/lib/Target/Cpu0/TargetInfo/CMakeLists.txt b/llvm/lib/Target/Cpu0/TargetInfo/CMakeLists.txt
new file mode 100644
index 00000000000000..d62a8eb042a6f2
--- /dev/null
+++ b/llvm/lib/Target/Cpu0/TargetInfo/CMakeLists.txt
@@ -0,0 +1,7 @@
+add_llvm_component_library(LLVMCpu0Info
+ Cpu0TargetInfo.cpp
+
+ LINK_COMPONENTS
+ MC
+ Support
+ )
\ No newline at end of file
diff --git a/llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.cpp b/llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.cpp
new file mode 100644
index 00000000000000..72380ee68bb32e
--- /dev/null
+++ b/llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.cpp
@@ -0,0 +1,14 @@
+#include "TargetInfo/Cpu0TargetInfo.h"
+#include "llvm/MC/TargetRegistry.h"
+using namespace llvm;
+
+Target &llvm::getTheCpu0Target() {
+ static Target TheCpu0Target;
+ return TheCpu0Target;
+}
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCpu0TargetInfo() {
+ RegisterTarget<Triple::cpu0,
+ /*HasJIT=*/true>
+ X(getTheCpu0Target(), "cpu0", "CPU0 (32-bit big endian)", "Cpu0");
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.h b/llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.h
new file mode 100644
index 00000000000000..212fc113099845
--- /dev/null
+++ b/llvm/lib/Target/Cpu0/TargetInfo/Cpu0TargetInfo.h
@@ -0,0 +1,12 @@
+#ifndef LLVM_LIB_TARGET_CPU0_TARGETINFO_CPU0TARGETINFO_H
+#define LLVM_LIB_TARGET_CPU0_TARGETINFO_CPU0TARGETINFO_H
+
+namespace llvm {
+
+class Target;
+
+Target &getTheCpu0Target();
+
+}
+
+#endif
\ No newline at end of file
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index ed58e72089839b..6144b41900d685 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -51,6 +51,7 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
case mips64el: return "mips64el";
case mips: return "mips";
case mipsel: return "mipsel";
+ case cpu0: return "cpu0";
case msp430: return "msp430";
case nvptx64: return "nvptx64";
case nvptx: return "nvptx";
@@ -194,6 +195,8 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
case mips64:
case mips64el: return "mips";
+ case cpu0: return "cpu0";
+
case hexagon: return "hexagon";
case amdgcn: return "amdgcn";
@@ -951,6 +954,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
case Triple::mips64:
case Triple::mips64el:
case Triple::mips:
+ case Triple::cpu0:
case Triple::msp430:
case Triple::nvptx64:
case Triple::nvptx:
@@ -1662,6 +1666,7 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::m68k:
case llvm::Triple::mips:
case llvm::Triple::mipsel:
+ case llvm::Triple::cpu0:
case llvm::Triple::nvptx:
case llvm::Triple::ppc:
case llvm::Triple::ppcle:
@@ -1752,6 +1757,7 @@ Triple Triple::get32BitArchVariant() const {
case Triple::m68k:
case Triple::mips:
case Triple::mipsel:
+ case Triple::cpu0:
case Triple::nvptx:
case Triple::ppc:
case Triple::ppcle:
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