[llvm] fb3fa41 - MachineRegisterInfo: Use variable for TRI

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2025-01-23T20:29:25+07:00
New Revision: fb3fa41aee4733e549620a4aa444525aacb075f7

URL: https://github.com/llvm/llvm-project/commit/fb3fa41aee4733e549620a4aa444525aacb075f7
DIFF: https://github.com/llvm/llvm-project/commit/fb3fa41aee4733e549620a4aa444525aacb075f7.diff

LOG: MachineRegisterInfo: Use variable for TRI

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index f058445cc556dc..937f63f6c5e004 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -122,8 +122,8 @@ bool
 MachineRegisterInfo::recomputeRegClass(Register Reg) {
   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
   const TargetRegisterClass *OldRC = getRegClass(Reg);
-  const TargetRegisterClass *NewRC =
-      getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
+  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
+  const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC, *MF);
 
   // Stop early if there is no room to grow.
   if (NewRC == OldRC)
@@ -134,8 +134,7 @@ MachineRegisterInfo::recomputeRegClass(Register Reg) {
     // Apply the effect of the given operand to NewRC.
     MachineInstr *MI = MO.getParent();
     unsigned OpNo = &MO - &MI->getOperand(0);
-    NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
-                                            getTargetRegisterInfo());
+    NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, TRI);
     if (!NewRC || NewRC == OldRC)
       return false;
   }