[llvm] [AArch64][SelectionDAG] Add CodeGen support for FEAT_CPA (PR #105669)

[Rodolfo Wottrich via llvm-commits]

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@@ -4081,8 +4087,15 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
       // For PIC, the sequence is:
       // BRIND(load(Jumptable + index) + RelocBase)
       // RelocBase can be JumpTable, GOT or some sort of global base.
-      Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
-                          TLI.getPICJumpTableRelocBase(Table, DAG));
+      if (!DAG.getTarget().shouldPreservePtrArith(
+              DAG.getMachineFunction().getFunction())) {
+        Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
+                           TLI.getPICJumpTableRelocBase(Table, DAG));
+      } else {
+        // PTRADD always takes the pointer first, so the operands are commuted
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rgwott wrote:

Emitting in the same order would break 20+ tests of several architectures. Although that is probably a simple problem, I do not believe fixing it should be in the scope of this PR. I changed `getMemBasePlusOffset()` to take an optional argument to allow the order of the operands to be inverted.

https://github.com/llvm/llvm-project/pull/105669