[llvm] [AArch64][SME] Spill p-regs as z-regs when streaming hazards are possible (PR #123752)

[Sander de Smalen via llvm-commits]

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@@ -397,6 +402,23 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, StringRef CPU,
   EnableSubregLiveness = EnableSubregLivenessTracking.getValue();
 }
 
+unsigned AArch64Subtarget::getHwModeSet() const {
+  unsigned Modes = 0;
+
+  // Use a special hardware mode in streaming functions with stack hazards.
+  // This changes the spill size (and alignment) for the predicate register
+  // class.
+  //
+  // FIXME: This overrides the table-gen'd `getHwModeSet()` which only looks at
+  // CPU features.
+  if (EnableZPRPredicateSpills.getValue() &&
+      (isStreaming() || isStreamingCompatible())) {
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sdesmalen-arm wrote:

This is related to the hazard size, so this needs a check that hazard size > 0.

https://github.com/llvm/llvm-project/pull/123752