[llvm] [AArch64][SME] Spill p-regs as z-regs when streaming hazards are possible (PR #123752)

[Sander de Smalen via llvm-commits]

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@@ -979,10 +979,19 @@ class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
 //******************************************************************************
 
 // SVE predicate register classes.
+
+// Note: This hardware mode is enabled in AArch64Subtarget::getHwModeSet()
+// (without the use of the table-gen'd predicates).
+def SMEWithStreamingMemoryHazards : HwMode<"", [Predicate<"false">]>;
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sdesmalen-arm wrote:

Does this not have to check the bitmask to verify bit `0` is set? (as you've set it in AArch64Subtarget)

https://github.com/llvm/llvm-project/pull/123752