[llvm] MachineCSE: Remove check for subreg on a def operand (PR #124095)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/124095

There are no subregister defs in SSA.

>From 01861c51eb2c6015a1ecbe50e52646e6d05b22b8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 23 Jan 2025 14:50:20 +0700
Subject: [PATCH] MachineCSE: Remove check for subreg on a def operand

There are no subregister defs in SSA.
---
 llvm/lib/CodeGen/MachineCSE.cpp | 2 --
 1 file changed, 2 deletions(-)

diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 728fd2f5f7cd4f..bea0eaf206f5ee 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -187,8 +187,6 @@ bool MachineCSEImpl::PerformTrivialCopyPropagation(MachineInstr *MI,
     Register SrcReg = DefMI->getOperand(1).getReg();
     if (!SrcReg.isVirtual())
       continue;
-    if (DefMI->getOperand(0).getSubReg())
-      continue;
     // FIXME: We should trivially coalesce subregister copies to expose CSE
     // opportunities on instructions with truncated operands (see
     // cse-add-with-overflow.ll). This can be done here as follows: