[llvm] [AArch64] Codegen for new SCVTF/UCVTF variants (FEAT_FPRCVT) (PR #123767)

[Virginia Cangelosi via llvm-commits]

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@@ -5511,6 +5511,15 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
     let Inst{31} = 1; // 64-bit FPR flag
     let Inst{23-22} = 0b00; // 32-bit FPR flag
   }
+
+  def : Pat<(f16 (any_fpround (f32 (op (i32 FPR32:$Rn))))),
+          (!cast<Instruction>(NAME # HSr) $Rn)>;
+  def : Pat<(f64 (op (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
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virginia-cangelosi wrote:

I have tried to change the pattern to accept any integer but haven't been successful. I also haven't found any examples of patterns which use this. Most patterns I've seen with extractelt use (i64 0)
When I try adding a test with %extract = extractelement <4 x i32> %x, i64 1, i get this:
        mov     w8, v0.s[1]
        scvtf   h0, w8
        ret
So it uses the old version as its loaded the 1 into a GPR    


https://github.com/llvm/llvm-project/pull/123767