[llvm] [AMDGPU] Update AMDGPUUsage.rst to document two intrinsics (PR #123816)

[Matt Arsenault via llvm-commits]

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@@ -1422,6 +1422,18 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
                                                    Returns a pair for the swapped registers. The first element of the return
                                                    corresponds to the swapped element of the first argument.
 
+  llvm.amdgcn.mov.dpp                              The llvm.amdgcn.mov.dpp.i32 intrinsic represents the mov.dpp operation in AMDGPU.
+                                                   This operation is being deprecated and can be replaced with llvm.amdgcn.update.dpp.
+
+  llvm.amdgcn.update.dpp                           The llvm.amdgcn.update.dpp intrinsic represents the update.dpp operation in AMDGPU.
+                                                   It takes an old value, a source operand, a DPP control operand, a row mask, a bank mask, and a bound control.
+                                                   This operation is equivalent to a sequence of v_mov_b32 operations.
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arsenm wrote:

Should mention it's v_mov_b32 with DPP, and mention the types it supports 

https://github.com/llvm/llvm-project/pull/123816