[llvm] [RISCV] Add SiFive sf.vqmacc tests to vmv-copy.mir. NFC (PR #124075)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/124075

Te vqmaccu.2x8x2 test is currently being miscompiled. We need to use a whole register move instead of vmv.v.v. The input has VL elements with EEW=8 EMUL=4. The output has VL/4 elements with EEW=32 EMUL=4. We can't use the original VL a vmv.v.v.

>From 871a3df182ec60da120bd15b10b3836d0981c04f Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 22 Jan 2025 21:54:43 -0800
Subject: [PATCH] [RISCV] Add SiFive sf.vqmacc tests to vmv-copy.mir. NFC

Te vqmaccu.2x8x2 test is currently being miscompiled. We need
to use a whole register move instead of vmv.v.v. The input has
VL elements with EEW=8 EMUL=4. The output has VL/4 elements with
EEW=32 EMUL=4. We can't use the original VL a vmv.v.v.
---
 llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir | 32 ++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir b/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
index f7d5004e11752f..bde289909271a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
@@ -280,6 +280,38 @@ body:             |
     $v24_v25_v26_v27_v28_v29_v30_v31 = COPY killed $v8_v9_v10_v11_v12_v13_v14_v15
 ...
 ---
+name: copy_sifive_custom_macc
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m4
+    ; CHECK-LABEL: name: copy_sifive_custom_macc
+    ; CHECK: liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 66 /* e8, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
+    ; CHECK-NEXT: $v4m4 = PseudoVQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $v16m4 = PseudoVMV_V_V_M4 undef $v16m4, $v4m4, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+    $x0 = PseudoVSETVLI  $x10, 66, implicit-def $vl, implicit-def $vtype
+    $v4m4 = PseudoVQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg, 3, 1, implicit $vl, implicit $vtype
+    $v16m4 = COPY renamable $v4m4
+...
+---
+name: copy_sifive_custom_macc1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m2
+    ; CHECK-LABEL: name: copy_sifive_custom_macc1
+    ; CHECK: liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 65 /* e8, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
+    ; CHECK-NEXT: $v4m4 = PseudoVQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
+    ; CHECK-NEXT: $v16m4 = VMV4R_V $v4m4, implicit $vtype
+    $x0 = PseudoVSETVLI  $x10, 65, implicit-def $vl, implicit-def $vtype
+    $v4m4 = PseudoVQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg, 3, 1, implicit $vl, implicit $vtype
+    $v16m4 = COPY renamable $v4m4
+...
+---
 name: copy_narrow_copies_in_between
 tracksRegLiveness: true
 body:             |