[llvm] [TableGen] Make sure BitWidth is set evem if all instructions are Pseudo or TargetOpcode (PR #124071)

[Farzon Lotfi via llvm-commits]

https://github.com/farzonl created https://github.com/llvm/llvm-project/pull/124071

## Bug
If all instruction records are TargetOpcode or isPseudo we never grows BitWidth above zero.

## Why
The reason why it is like this is because TargetOpcode do not have an Inst field.

## The problem
That causes a compile error because InstBits is just full of commas with no data in the array.

## Fix
On line 487 Set BitWidth to 1.

fixes #124067

>From e5e94fda88231e06733dcb5070f23d4ce4704007 Mon Sep 17 00:00:00 2001
From: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: Thu, 23 Jan 2025 00:47:07 -0500
Subject: [PATCH] [TableGen] Make sure BitWidth is set evem if all instructions
 are Pseudo or TargetOpcode fixes #124067

---
 llvm/test/TableGen/OnlyPseudoInst.td   | 25 +++++++++++++++++++++++++
 llvm/utils/TableGen/CodeEmitterGen.cpp |  2 +-
 2 files changed, 26 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/TableGen/OnlyPseudoInst.td

diff --git a/llvm/test/TableGen/OnlyPseudoInst.td b/llvm/test/TableGen/OnlyPseudoInst.td
new file mode 100644
index 00000000000000..56baf53bc70e3b
--- /dev/null
+++ b/llvm/test/TableGen/OnlyPseudoInst.td
@@ -0,0 +1,25 @@
+
+// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | \
+// RUN:     FileCheck %s --check-prefix=ENCODER
+
+include "llvm/Target/Target.td"
+
+def archInstrInfo : InstrInfo { }
+
+def arch : Target {
+  let InstructionSet = archInstrInfo;
+}
+
+class PseudoInst<bits<16> Opcode> : Instruction {
+  field bits<16> Inst;
+  let Inst = Opcode;
+  dag OutOperandList = (outs);
+  dag InOperandList =  (ins);
+  let Pattern = [];
+  let isPseudo = 1;
+}
+
+def DummyInst : PseudoInst<0>;
+
+// ENCODER-LABEL:   static const uint64_t InstBits[] = {
+// ENCODER:         UINT64_C(0),
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 475699ae3e78e9..77fedee0cf4c35 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -484,7 +484,7 @@ void CodeEmitterGen::run(raw_ostream &O) {
     const CodeGenHwModes &HWM = Target.getHwModes();
     // The set of HwModes used by instruction encodings.
     std::set<unsigned> HwModes;
-    BitWidth = 0;
+    BitWidth = 1;
     for (const CodeGenInstruction *CGI : NumberedInstructions) {
       const Record *R = CGI->TheDef;
       if (R->getValueAsString("Namespace") == "TargetOpcode" ||