[llvm] [RISCV] Add register allocation hints for lui/auipc+addi fusion. (PR #123860)

[Philip Reames via llvm-commits]

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@@ -926,6 +926,26 @@ bool RISCVRegisterInfo::getRegAllocationHints(
         tryAddHint(MO, MI.getOperand(0), NeedGPRC);
       }
     }
+
+    // Add a hint if it would allow auipc/lui+addi(w) fusion.
+    if ((MI.getOpcode() == RISCV::ADDIW || MI.getOpcode() == RISCV::ADDI) &&
+        MI.getOperand(1).isReg()) {
+      const MachineBasicBlock &MBB = *MI.getParent();
+      MachineBasicBlock::const_iterator I = MI.getIterator();
+      // Is the previous instruction a LUI or AUIPC that can be fused?
+      if (I != MBB.begin()) {
+        I = skipDebugInstructionsBackward(std::prev(I), MBB.begin());
+        if (((I->getOpcode() == RISCV::LUI && Subtarget.hasLUIADDIFusion()) ||
----------------
preames wrote:

I wonder where these two fusions are general/common enough that we should just enable this by default.  Even for code not sufficiently compiled with such a fusion in mind, it has a high chance of running on a machine with these fusions.  Though I guess, this is really more asking if this should be in the generic tuning, and is a bit orthogonal from this patch isn't it?

https://github.com/llvm/llvm-project/pull/123860