[llvm] 146ee98 - [RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865)

[via llvm-commits]

Author: Craig Topper
Date: 2025-01-22T10:37:01-08:00
New Revision: 146ee98caa9ab1f717216b08cfe72bd1ab2e0b8b

URL: https://github.com/llvm/llvm-project/commit/146ee98caa9ab1f717216b08cfe72bd1ab2e0b8b
DIFF: https://github.com/llvm/llvm-project/commit/146ee98caa9ab1f717216b08cfe72bd1ab2e0b8b.diff

LOG: [RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865)

We had two WriteRes for WriteJalr with difference latencies. Drop the
duplicate and change the latency of Jal to 1 based on review feedback

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
index a8e8de24979887..a1127966e8417d 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
@@ -125,11 +125,8 @@ def : WriteRes<WriteCSR, [p8700ALQ]>;
 
 // Handle CTI Pipeline.
 def : WriteRes<WriteJmp, [p8700IssueCTI]>;
-def : WriteRes<WriteJalr, [p8700IssueCTI]>;
-let Latency = 2 in {
 def : WriteRes<WriteJal, [p8700IssueCTI]>;
 def : WriteRes<WriteJalr, [p8700IssueCTI]>;
-}
 
 // Handle FPU Pipelines.
 def p8700FPQ : ProcResource<3> { let BufferSize = 16; }