[llvm] [RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (PR #123865)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 22 09:16:31 PST 2025


https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/123865

>From 1e61a62cbf4b8800fbb6edef7c9a3e2744482a38 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 21 Jan 2025 17:42:48 -0800
Subject: [PATCH 1/2] [RISCV] Remove duplicate WriteRes<WriteJalr for
 MIPSP8700.

We had two WriteRes for WriteJalr with difference latencies. I don't
know which is correct. I chose Latency=2 to match WriteJal.
---
 llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 -
 1 file changed, 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
index 550f83a59b8b0e..ab6402dc96af10 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
@@ -125,7 +125,6 @@ def : WriteRes<WriteCSR, [p8700ALQ]>;
 
 // Handle CTI Pipeline.
 def : WriteRes<WriteJmp, [p8700IssueCTI]>;
-def : WriteRes<WriteJalr, [p8700IssueCTI]>;
 let Latency = 2 in {
 def : WriteRes<WriteJal, [p8700IssueCTI]>;
 def : WriteRes<WriteJalr, [p8700IssueCTI]>;

>From f4388156c1524b145a9e824585c130573469615a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 22 Jan 2025 09:14:42 -0800
Subject: [PATCH 2/2] fixup! Remove Latency=2

---
 llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 2 --
 1 file changed, 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
index ab6402dc96af10..9dbd7e55e3a5d2 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
@@ -125,10 +125,8 @@ def : WriteRes<WriteCSR, [p8700ALQ]>;
 
 // Handle CTI Pipeline.
 def : WriteRes<WriteJmp, [p8700IssueCTI]>;
-let Latency = 2 in {
 def : WriteRes<WriteJal, [p8700IssueCTI]>;
 def : WriteRes<WriteJalr, [p8700IssueCTI]>;
-}
 
 // Handle FPU Pipelines.
 def p8700FPQ : ProcResource<3> { let BufferSize = 16; }



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