[llvm] 13d09df - [X86] Simplify ArrayRef construction. NFC (#123899)

[via llvm-commits]

Author: Craig Topper
Date: 2025-01-22T09:07:58-08:00
New Revision: 13d09dfad6d1f6a15721688822ce33b74b44a8d8

URL: https://github.com/llvm/llvm-project/commit/13d09dfad6d1f6a15721688822ce33b74b44a8d8
DIFF: https://github.com/llvm/llvm-project/commit/13d09dfad6d1f6a15721688822ce33b74b44a8d8.diff

LOG: [X86] Simplify ArrayRef construction. NFC (#123899)

I think the std::begin/end were to work around an old gcc bug. Hopefully
we don't need them anymore.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86CallingConv.cpp
    llvm/lib/Target/X86/X86ISelLoweringCall.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86CallingConv.cpp b/llvm/lib/Target/X86/X86CallingConv.cpp
index b85d9d9a7e535b..7359ef341dde58 100644
--- a/llvm/lib/Target/X86/X86CallingConv.cpp
+++ b/llvm/lib/Target/X86/X86CallingConv.cpp
@@ -68,23 +68,23 @@ static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) {
   if (ValVT.is512BitVector()) {
     static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2,
                                            X86::ZMM3, X86::ZMM4, X86::ZMM5};
-    return ArrayRef(std::begin(RegListZMM), std::end(RegListZMM));
+    return RegListZMM;
   }
 
   if (ValVT.is256BitVector()) {
     static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2,
                                            X86::YMM3, X86::YMM4, X86::YMM5};
-    return ArrayRef(std::begin(RegListYMM), std::end(RegListYMM));
+    return RegListYMM;
   }
 
   static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2,
                                          X86::XMM3, X86::XMM4, X86::XMM5};
-  return ArrayRef(std::begin(RegListXMM), std::end(RegListXMM));
+  return RegListXMM;
 }
 
 static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() {
   static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9};
-  return ArrayRef(std::begin(RegListGPR), std::end(RegListGPR));
+  return RegListGPR;
 }
 
 static bool CC_X86_VectorCallAssignRegister(unsigned &ValNo, MVT &ValVT,

diff  --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
index 10aa2a5e5dac8a..4a4fd246cb7cdf 100644
--- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
@@ -1416,13 +1416,13 @@ static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
     static const MCPhysReg GPR64ArgRegsWin64[] = {
       X86::RCX, X86::RDX, X86::R8,  X86::R9
     };
-    return ArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
+    return GPR64ArgRegsWin64;
   }
 
   static const MCPhysReg GPR64ArgRegs64Bit[] = {
     X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
   };
-  return ArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
+  return GPR64ArgRegs64Bit;
 }
 
 // FIXME: Get this from tablegen.
@@ -1448,7 +1448,7 @@ static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
     X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
     X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
   };
-  return ArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
+  return XMMArgRegs64Bit;
 }
 
 #ifndef NDEBUG