[llvm] c6c6475 - [SLP][NFC] Update test for PR #118055 (#122696)
via llvm-commits
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Wed Jan 22 03:28:38 PST 2025
Author: Sushant Gokhale
Date: 2025-01-22T03:28:34-08:00
New Revision: c6c647588f911770170d2f7975b325f3d70cf89b
URL: https://github.com/llvm/llvm-project/commit/c6c647588f911770170d2f7975b325f3d70cf89b
DIFF: https://github.com/llvm/llvm-project/commit/c6c647588f911770170d2f7975b325f3d70cf89b.diff
LOG: [SLP][NFC] Update test for PR #118055 (#122696)
This patch updates the motivating test for the above PR so that it does
not conflict with urem PR #122236
Added:
Modified:
llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
index 57c877a58d5c0e..29bd81998cdb2a 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
@@ -552,9 +552,62 @@ define <4 x i32> @slp_v4i32_Op1_unknown_Op2_const_pow2(<4 x i32> %a)
ret <4 x i32> %r3
}
+define <2 x i32> @sdiv_v2i32_unknown_divisor(<2 x i32> %a, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
+; NO-SVE-LABEL: define <2 x i32> @sdiv_v2i32_unknown_divisor(
+; NO-SVE-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]]) #[[ATTR0]] {
+; NO-SVE-NEXT: [[A0:%.*]] = extractelement <2 x i32> [[A]], i64 0
+; NO-SVE-NEXT: [[A1:%.*]] = extractelement <2 x i32> [[A]], i64 1
+; NO-SVE-NEXT: [[X0:%.*]] = extractelement <2 x i32> [[X]], i64 0
+; NO-SVE-NEXT: [[X1:%.*]] = extractelement <2 x i32> [[X]], i64 1
+; NO-SVE-NEXT: [[TMP1:%.*]] = sdiv i32 [[A0]], [[X0]]
+; NO-SVE-NEXT: [[TMP2:%.*]] = sdiv i32 [[A1]], [[X1]]
+; NO-SVE-NEXT: [[TMP3:%.*]] = add i32 [[TMP1]], [[X0]]
+; NO-SVE-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], [[X1]]
+; NO-SVE-NEXT: [[Y0:%.*]] = extractelement <2 x i32> [[Y]], i64 0
+; NO-SVE-NEXT: [[Y1:%.*]] = extractelement <2 x i32> [[Y]], i64 1
+; NO-SVE-NEXT: [[TMP5:%.*]] = sub i32 [[TMP3]], [[Y0]]
+; NO-SVE-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[Y1]]
+; NO-SVE-NEXT: [[Z0:%.*]] = extractelement <2 x i32> [[Z]], i64 0
+; NO-SVE-NEXT: [[Z1:%.*]] = extractelement <2 x i32> [[Z]], i64 1
+; NO-SVE-NEXT: [[TMP7:%.*]] = mul i32 [[TMP5]], [[Z0]]
+; NO-SVE-NEXT: [[TMP8:%.*]] = mul i32 [[TMP6]], [[Z1]]
+; NO-SVE-NEXT: [[RES0:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i32 0
+; NO-SVE-NEXT: [[RES1:%.*]] = insertelement <2 x i32> [[RES0]], i32 [[TMP8]], i32 1
+; NO-SVE-NEXT: ret <2 x i32> [[RES1]]
+;
+; SVE-LABEL: define <2 x i32> @sdiv_v2i32_unknown_divisor(
+; SVE-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]]) #[[ATTR0]] {
+; SVE-NEXT: [[TMP2:%.*]] = sdiv <2 x i32> [[A]], [[X]]
+; SVE-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], [[X]]
+; SVE-NEXT: [[TMP4:%.*]] = sub <2 x i32> [[TMP3]], [[Y]]
+; SVE-NEXT: [[TMP5:%.*]] = mul <2 x i32> [[TMP4]], [[Z]]
+; SVE-NEXT: ret <2 x i32> [[TMP5]]
+;
+{
+ %a0 = extractelement <2 x i32> %a, i64 0
+ %a1 = extractelement <2 x i32> %a, i64 1
+ %x0 = extractelement <2 x i32> %x, i64 0
+ %x1 = extractelement <2 x i32> %x, i64 1
+ %1 = sdiv i32 %a0, %x0
+ %2 = sdiv i32 %a1, %x1
+ %3 = add i32 %1, %x0
+ %4 = add i32 %2, %x1
+ %y0 = extractelement <2 x i32> %y, i64 0
+ %y1 = extractelement <2 x i32> %y, i64 1
+ %5 = sub i32 %3, %y0
+ %6 = sub i32 %4, %y1
+ %z0 = extractelement <2 x i32> %z, i64 0
+ %z1 = extractelement <2 x i32> %z, i64 1
+ %7 = mul i32 %5, %z0
+ %8 = mul i32 %6, %z1
+ %res0 = insertelement <2 x i32> poison, i32 %7, i32 0
+ %res1 = insertelement <2 x i32> %res0, i32 %8, i32 1
+ ret <2 x i32> %res1
+}
+
; computes (a/const + x - y) * z
-define <2 x i32> @vectorize_sdiv_v2i32(<2 x i32> %a, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
-; NO-SVE-LABEL: define <2 x i32> @vectorize_sdiv_v2i32(
+define <2 x i32> @sdiv_v2i32_const_divisor(<2 x i32> %a, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
+; NO-SVE-LABEL: define <2 x i32> @sdiv_v2i32_const_divisor(
; NO-SVE-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]]) #[[ATTR0]] {
; NO-SVE-NEXT: [[A0:%.*]] = extractelement <2 x i32> [[A]], i64 0
; NO-SVE-NEXT: [[A1:%.*]] = extractelement <2 x i32> [[A]], i64 1
@@ -576,7 +629,7 @@ define <2 x i32> @vectorize_sdiv_v2i32(<2 x i32> %a, <2 x i32> %x, <2 x i32> %y,
; NO-SVE-NEXT: [[RES1:%.*]] = insertelement <2 x i32> [[RES0]], i32 [[TMP8]], i32 1
; NO-SVE-NEXT: ret <2 x i32> [[RES1]]
;
-; SVE-LABEL: define <2 x i32> @vectorize_sdiv_v2i32(
+; SVE-LABEL: define <2 x i32> @sdiv_v2i32_const_divisor(
; SVE-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]]) #[[ATTR0]] {
; SVE-NEXT: [[TMP1:%.*]] = sdiv <2 x i32> [[A]], <i32 2, i32 4>
; SVE-NEXT: [[TMP2:%.*]] = add <2 x i32> [[TMP1]], [[X]]
@@ -605,3 +658,57 @@ define <2 x i32> @vectorize_sdiv_v2i32(<2 x i32> %a, <2 x i32> %x, <2 x i32> %y,
%res1 = insertelement <2 x i32> %res0, i32 %8, i32 1
ret <2 x i32> %res1
}
+
+define <2 x i32> @sdiv_v2i32_Op1_unknown_Op2_const(<2 x i32> %a, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
+; NO-SVE-LABEL: define <2 x i32> @sdiv_v2i32_Op1_unknown_Op2_const(
+; NO-SVE-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]]) #[[ATTR0]] {
+; NO-SVE-NEXT: [[A0:%.*]] = extractelement <2 x i32> [[A]], i64 0
+; NO-SVE-NEXT: [[A1:%.*]] = extractelement <2 x i32> [[A]], i64 1
+; NO-SVE-NEXT: [[TMP1:%.*]] = sdiv i32 [[A0]], [[A0]]
+; NO-SVE-NEXT: [[TMP2:%.*]] = sdiv i32 [[A1]], 4
+; NO-SVE-NEXT: [[X0:%.*]] = extractelement <2 x i32> [[X]], i64 0
+; NO-SVE-NEXT: [[X1:%.*]] = extractelement <2 x i32> [[X]], i64 1
+; NO-SVE-NEXT: [[TMP3:%.*]] = add i32 [[TMP1]], [[X0]]
+; NO-SVE-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], [[X1]]
+; NO-SVE-NEXT: [[Y0:%.*]] = extractelement <2 x i32> [[Y]], i64 0
+; NO-SVE-NEXT: [[Y1:%.*]] = extractelement <2 x i32> [[Y]], i64 1
+; NO-SVE-NEXT: [[TMP5:%.*]] = sub i32 [[TMP3]], [[Y0]]
+; NO-SVE-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[Y1]]
+; NO-SVE-NEXT: [[Z0:%.*]] = extractelement <2 x i32> [[Z]], i64 0
+; NO-SVE-NEXT: [[Z1:%.*]] = extractelement <2 x i32> [[Z]], i64 1
+; NO-SVE-NEXT: [[TMP7:%.*]] = mul i32 [[TMP5]], [[Z0]]
+; NO-SVE-NEXT: [[TMP8:%.*]] = mul i32 [[TMP6]], [[Z1]]
+; NO-SVE-NEXT: [[RES0:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i32 0
+; NO-SVE-NEXT: [[RES1:%.*]] = insertelement <2 x i32> [[RES0]], i32 [[TMP8]], i32 1
+; NO-SVE-NEXT: ret <2 x i32> [[RES1]]
+;
+; SVE-LABEL: define <2 x i32> @sdiv_v2i32_Op1_unknown_Op2_const(
+; SVE-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]]) #[[ATTR0]] {
+; SVE-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> <i32 poison, i32 4>, <2 x i32> <i32 0, i32 3>
+; SVE-NEXT: [[TMP2:%.*]] = sdiv <2 x i32> [[A]], [[TMP1]]
+; SVE-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], [[X]]
+; SVE-NEXT: [[TMP4:%.*]] = sub <2 x i32> [[TMP3]], [[Y]]
+; SVE-NEXT: [[TMP5:%.*]] = mul <2 x i32> [[TMP4]], [[Z]]
+; SVE-NEXT: ret <2 x i32> [[TMP5]]
+;
+{
+ %a0 = extractelement <2 x i32> %a, i64 0
+ %a1 = extractelement <2 x i32> %a, i64 1
+ %1 = sdiv i32 %a0, %a0
+ %2 = sdiv i32 %a1, 4
+ %x0 = extractelement <2 x i32> %x, i64 0
+ %x1 = extractelement <2 x i32> %x, i64 1
+ %3 = add i32 %1, %x0
+ %4 = add i32 %2, %x1
+ %y0 = extractelement <2 x i32> %y, i64 0
+ %y1 = extractelement <2 x i32> %y, i64 1
+ %5 = sub i32 %3, %y0
+ %6 = sub i32 %4, %y1
+ %z0 = extractelement <2 x i32> %z, i64 0
+ %z1 = extractelement <2 x i32> %z, i64 1
+ %7 = mul i32 %5, %z0
+ %8 = mul i32 %6, %z1
+ %res0 = insertelement <2 x i32> poison, i32 %7, i32 0
+ %res1 = insertelement <2 x i32> %res0, i32 %8, i32 1
+ ret <2 x i32> %res1
+}
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