[llvm] d03fab1 - [RISCV] Add precommit test for #123882
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 22 03:08:52 PST 2025
Author: Wang Pengcheng
Date: 2025-01-22T19:08:39+08:00
New Revision: d03fab1be38508f2a732330242a14744e4907ff9
URL: https://github.com/llvm/llvm-project/commit/d03fab1be38508f2a732330242a14744e4907ff9
DIFF: https://github.com/llvm/llvm-project/commit/d03fab1be38508f2a732330242a14744e4907ff9.diff
LOG: [RISCV] Add precommit test for #123882
Add MCA test for jump instructions.
Added:
llvm/test/tools/llvm-mca/RISCV/SiFive7/jump.s
Modified:
Removed:
################################################################################
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/jump.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/jump.s
new file mode 100644
index 00000000000000..3623d92311ae9a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/jump.s
@@ -0,0 +1,81 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-u74 -timeline -iterations=1 < %s \
+# RUN: | FileCheck %s
+
+jal x0, 1f
+1:
+jal a0, 1f
+1:
+jalr x0, a0
+jalr t0, a0
+ret
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 5
+# CHECK-NEXT: Total Cycles: 10
+# CHECK-NEXT: Total uOps: 5
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.50
+# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: Block RThroughput: 5.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 j .Ltmp0
+# CHECK-NEXT: 1 3 1.00 jal a0, .Ltmp1
+# CHECK-NEXT: 1 3 1.00 jr a0
+# CHECK-NEXT: 1 3 1.00 jalr t0, a0
+# CHECK-NEXT: 1 3 1.00 ret
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFive7FDiv
+# CHECK-NEXT: [1] - SiFive7IDiv
+# CHECK-NEXT: [2] - SiFive7PipeA
+# CHECK-NEXT: [3] - SiFive7PipeB
+# CHECK-NEXT: [4] - SiFive7VA
+# CHECK-NEXT: [5] - SiFive7VCQ
+# CHECK-NEXT: [6] - SiFive7VL
+# CHECK-NEXT: [7] - SiFive7VS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# CHECK-NEXT: - - - 5.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - - 1.00 - - - - j .Ltmp0
+# CHECK-NEXT: - - - 1.00 - - - - jal a0, .Ltmp1
+# CHECK-NEXT: - - - 1.00 - - - - jr a0
+# CHECK-NEXT: - - - 1.00 - - - - jalr t0, a0
+# CHECK-NEXT: - - - 1.00 - - - - ret
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeE . . j .Ltmp0
+# CHECK-NEXT: [0,1] .DeeE. . jal a0, .Ltmp1
+# CHECK-NEXT: [0,2] . DeeE . jr a0
+# CHECK-NEXT: [0,3] . DeeE. jalr t0, a0
+# CHECK-NEXT: [0,4] . .DeeE ret
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 0.0 0.0 0.0 j .Ltmp0
+# CHECK-NEXT: 1. 1 0.0 0.0 0.0 jal a0, .Ltmp1
+# CHECK-NEXT: 2. 1 0.0 0.0 0.0 jr a0
+# CHECK-NEXT: 3. 1 0.0 0.0 0.0 jalr t0, a0
+# CHECK-NEXT: 4. 1 0.0 0.0 0.0 ret
+# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
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