[llvm] [RISCV][VLOPT] Don't reduce the VL is the same as CommonVL (PR #123878)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 21 20:51:10 PST 2025
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/123878
>From 3fe2f770e4ead1184f2399432a004bed8da8063c Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 21 Jan 2025 20:40:58 -0800
Subject: [PATCH 1/2] [RISCV][VLOPT] Don't reduce the VL is the same as
CommonVL
This fixes #123862.
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 7 +++++++
llvm/test/CodeGen/RISCV/rvv/vl-opt.ll | 11 +++++++++++
2 files changed, 18 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 54ca8ccd8d9e90..9182e1f751933c 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1320,6 +1320,13 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &OrigMI) {
}
if (CommonVL->isImm()) {
+ if (CommonVL->isImm() && VLOp.isImm() &&
+ VLOp.getImm() == CommonVL->getImm()) {
+ LLVM_DEBUG(dbgs() << " VL is already reduced to" << VLOp << " for "
+ << MI << "\n");
+ continue;
+ }
+
LLVM_DEBUG(dbgs() << " Reduce VL from " << VLOp << " to "
<< CommonVL->getImm() << " for " << MI << "\n");
VLOp.ChangeToImmediate(CommonVL->getImm());
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
index 1cc30f077feb4a..d6143f69288e66 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
@@ -150,3 +150,14 @@ define <vscale x 4 x i32> @dont_optimize_tied_def(<vscale x 4 x i32> %a, <vscale
ret <vscale x 4 x i32> %2
}
+define <vscale x 4 x i32> @same_vl_imm(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: same_vl_imm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vadd.vv v8, v10, v12
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 4)
+ %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen 4)
+ ret <vscale x 4 x i32> %w
+}
>From dab15d6f0022d9ae8a8be05ce1eb2fe267e4d865 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 21 Jan 2025 20:49:55 -0800
Subject: [PATCH 2/2] fixup! generalize to regs
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 15 +++++++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 3 +++
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 11 ++---------
llvm/test/CodeGen/RISCV/rvv/vl-opt.ll | 12 ++++++++++++
4 files changed, 32 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 1f7e8d87a11b0c..ac3b30866edf8b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4244,6 +4244,21 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
return LHS.getImm() <= RHS.getImm();
}
+/// Given two VL operands, do we know that LHS < RHS?
+bool RISCV::isVLKnownLT(const MachineOperand &LHS, const MachineOperand &RHS) {
+ if (LHS.isReg() && RHS.isReg() && LHS.getReg().isVirtual() &&
+ LHS.getReg() == RHS.getReg())
+ return false;
+ if (RHS.isImm() && RHS.getImm() == RISCV::VLMaxSentinel && LHS.isImm() &&
+ LHS.getImm() != RHS.getImm())
+ return true;
+ if (LHS.isImm() && LHS.getImm() == RISCV::VLMaxSentinel)
+ return false;
+ if (!LHS.isImm() || !RHS.isImm())
+ return false;
+ return LHS.getImm() < RHS.getImm();
+}
+
namespace {
class RISCVPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
const MachineInstr *LHS;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 7e8bcd451a8ef8..fed7fae6d932c4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -357,6 +357,9 @@ static constexpr int64_t VLMaxSentinel = -1LL;
/// Given two VL operands, do we know that LHS <= RHS?
bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS);
+/// Given two VL operands, do we know that LHS < RHS?
+bool isVLKnownLT(const MachineOperand &LHS, const MachineOperand &RHS);
+
// Mask assignments for floating-point
static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
static constexpr unsigned FPMASK_Negative_Normal = 0x002;
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 9182e1f751933c..42e44d66b3cf78 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1314,19 +1314,12 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &OrigMI) {
unsigned VLOpNum = RISCVII::getVLOpNum(MI.getDesc());
MachineOperand &VLOp = MI.getOperand(VLOpNum);
- if (!RISCV::isVLKnownLE(*CommonVL, VLOp)) {
- LLVM_DEBUG(dbgs() << " Abort due to CommonVL not <= VLOp.\n");
+ if (!RISCV::isVLKnownLT(*CommonVL, VLOp)) {
+ LLVM_DEBUG(dbgs() << " Abort due to CommonVL not < VLOp.\n");
continue;
}
if (CommonVL->isImm()) {
- if (CommonVL->isImm() && VLOp.isImm() &&
- VLOp.getImm() == CommonVL->getImm()) {
- LLVM_DEBUG(dbgs() << " VL is already reduced to" << VLOp << " for "
- << MI << "\n");
- continue;
- }
-
LLVM_DEBUG(dbgs() << " Reduce VL from " << VLOp << " to "
<< CommonVL->getImm() << " for " << MI << "\n");
VLOp.ChangeToImmediate(CommonVL->getImm());
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
index d6143f69288e66..2599571dd78532 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
@@ -161,3 +161,15 @@ define <vscale x 4 x i32> @same_vl_imm(<vscale x 4 x i32> %passthru, <vscale x 4
%w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen 4)
ret <vscale x 4 x i32> %w
}
+
+define <vscale x 4 x i32> @same_vl_reg(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
+; CHECK-LABEL: same_vl_reg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; CHECK-NEXT: vadd.vv v8, v10, v12
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: ret
+ %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl)
+ %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen %vl)
+ ret <vscale x 4 x i32> %w
+}
More information about the llvm-commits
mailing list