[llvm] [RISCV][VLOPT] Don't reduce the VL is the same as CommonVL (PR #123878)

Michael Maitland via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 21 20:46:25 PST 2025


https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/123878

This fixes #123862.

>From 3fe2f770e4ead1184f2399432a004bed8da8063c Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 21 Jan 2025 20:40:58 -0800
Subject: [PATCH] [RISCV][VLOPT] Don't reduce the VL is the same as CommonVL

This fixes #123862.
---
 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp |  7 +++++++
 llvm/test/CodeGen/RISCV/rvv/vl-opt.ll      | 11 +++++++++++
 2 files changed, 18 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 54ca8ccd8d9e90..9182e1f751933c 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1320,6 +1320,13 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &OrigMI) {
     }
 
     if (CommonVL->isImm()) {
+      if (CommonVL->isImm() && VLOp.isImm() &&
+          VLOp.getImm() == CommonVL->getImm()) {
+        LLVM_DEBUG(dbgs() << "  VL is already reduced to" << VLOp << " for "
+                          << MI << "\n");
+        continue;
+      }
+
       LLVM_DEBUG(dbgs() << "  Reduce VL from " << VLOp << " to "
                         << CommonVL->getImm() << " for " << MI << "\n");
       VLOp.ChangeToImmediate(CommonVL->getImm());
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
index 1cc30f077feb4a..d6143f69288e66 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
@@ -150,3 +150,14 @@ define <vscale x 4 x i32> @dont_optimize_tied_def(<vscale x 4 x i32> %a, <vscale
   ret <vscale x 4 x i32> %2
 }
 
+define <vscale x 4 x i32> @same_vl_imm(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: same_vl_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT:    vadd.vv v8, v10, v12
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    ret
+  %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 4)
+  %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen 4)
+  ret <vscale x 4 x i32> %w
+}



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