[llvm] [llvm][CodeGen] Fix the issue caused by live interval checking in window scheduler (PR #123184)
Hua Tian via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 21 20:21:39 PST 2025
https://github.com/huaatian updated https://github.com/llvm/llvm-project/pull/123184
>From 507d47c50e491cdaa56846f7265d8291a49bc4c9 Mon Sep 17 00:00:00 2001
From: akiratian <akiratian at tencent.com>
Date: Thu, 16 Jan 2025 19:06:49 +0800
Subject: [PATCH 1/6] [llvm][CodeGen] Fix the issue caused by live interval
checking in window scheduler
At some corner cases, the cloned MI still retains a random slot index,
which leads to the compiler crashing. Therefore, when we repair the slot
index of the newly cloned MI, we first clear it.
https://github.com/llvm/llvm-project/issues/123165
---
llvm/lib/CodeGen/WindowScheduler.cpp | 5 +-
.../Hexagon/swp-ws-live-intervals-1.mir | 61 +++++++++++++++++++
2 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index f1658e36ae1e92..56e92ff9bde7f5 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -645,7 +645,7 @@ void WindowScheduler::expand() {
void WindowScheduler::updateLiveIntervals() {
SmallVector<Register, 128> UsedRegs;
- for (MachineInstr &MI : *MBB)
+ for (MachineInstr &MI : *MBB) {
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || MO.getReg() == 0)
continue;
@@ -653,6 +653,9 @@ void WindowScheduler::updateLiveIntervals() {
if (!is_contained(UsedRegs, Reg))
UsedRegs.push_back(Reg);
}
+ // Remove the residual slot index of newly cloned MI.
+ Context->LIS->getSlotIndexes()->removeMachineInstrFromMaps(MI, true);
+ }
Context->LIS->repairIntervalsInRange(MBB, MBB->begin(), MBB->end(), UsedRegs);
}
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir b/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir
new file mode 100644
index 00000000000000..ae5e10b1eee1ff
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir
@@ -0,0 +1,61 @@
+# REQUIRES: asserts
+#
+# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1\
+# RUN: | FileCheck %s
+
+# The bug was reported at https://github.com/llvm/llvm-project/issues/123165.
+# It is caused by the corruption of live intervals in certain scenarios.
+#
+# We check window scheduling logs to ensure that there is no crashing.
+# CHECK: Start analyzing II:
+# CHECK: MaxCycle is {{[0-9]+}}.
+# CHECK: MaxStallCycle is {{[0-9]+}}.
+# CHECK: Start scheduling Phis:
+# CHECK: Current window Offset is {{[0-9]+}} and II is {{[0-9]+}}.
+# CHECK: Window scheduling is not needed!
+
+...
+---
+name: _ZN10CInArchive17GetNextFolderItemEv
+tracksRegLiveness: true
+body: |
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $r0
+
+ %0:intregs = COPY $r0
+ J2_loop0i %bb.1, 1, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+
+ bb.1:
+ successors: %bb.2(0x04000000), %bb.1(0x7c000000)
+
+ %1:intregs = L2_loadri_io %0, 0
+ %2:intregs = L2_loadrub_io killed %1, 0
+ %3:intregs = PS_loadriabs 0
+ S2_storerb_io killed %3, 0, killed %2
+ ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+
+ bb.2:
+ successors: %bb.4(0x80000000)
+
+ %4:intregs = A2_tfrsi 0
+ %5:intregs = A2_tfrsi -1
+ J2_loop0i %bb.4, 1, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+ J2_jump %bb.4, implicit-def $pc
+
+ bb.3:
+ S2_storeri_io %0, 0, %6
+ PS_jmpret $r31, implicit-def dead $pc
+
+ bb.4:
+ successors: %bb.3(0x04000000), %bb.4(0x7c000000)
+
+ %7:intregs = PHI %5, %bb.2, %8, %bb.4
+ %6:intregs = PHI %4, %bb.2, %9, %bb.4
+ %8:intregs = A2_addi %7, 1
+ %9:intregs = S2_setbit_i %8, 0
+ ENDLOOP0 %bb.4, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+ J2_jump %bb.3, implicit-def $pc
+
+...
>From 67b12ae722c2ce4edbae8103c6443a7c21a608e7 Mon Sep 17 00:00:00 2001
From: akiratian <akiratian at tencent.com>
Date: Fri, 17 Jan 2025 10:24:43 +0800
Subject: [PATCH 2/6] [llvm][CodeGen] Modifications made based on review
comments 1
---
llvm/lib/CodeGen/WindowScheduler.cpp | 6 +++---
llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 56e92ff9bde7f5..2177afcfab3ea1 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -270,7 +270,7 @@ void WindowScheduler::backupMBB() {
OriMIs.push_back(&MI);
// Remove MIs and the corresponding live intervals.
for (auto &MI : make_early_inc_range(*MBB)) {
- Context->LIS->getSlotIndexes()->removeMachineInstrFromMaps(MI, true);
+ Context->LIS->RemoveMachineInstrFromMaps(MI);
MBB->remove(&MI);
}
}
@@ -278,7 +278,7 @@ void WindowScheduler::backupMBB() {
void WindowScheduler::restoreMBB() {
// Erase MIs and the corresponding live intervals.
for (auto &MI : make_early_inc_range(*MBB)) {
- Context->LIS->getSlotIndexes()->removeMachineInstrFromMaps(MI, true);
+ Context->LIS->RemoveMachineInstrFromMaps(MI);
MI.eraseFromParent();
}
// Restore MBB to the state before window scheduling.
@@ -654,7 +654,7 @@ void WindowScheduler::updateLiveIntervals() {
UsedRegs.push_back(Reg);
}
// Remove the residual slot index of newly cloned MI.
- Context->LIS->getSlotIndexes()->removeMachineInstrFromMaps(MI, true);
+ Context->LIS->RemoveMachineInstrFromMaps(MI);
}
Context->LIS->repairIntervalsInRange(MBB, MBB->begin(), MBB->end(), UsedRegs);
}
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir b/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir
index ae5e10b1eee1ff..c43fce5707de88 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir
@@ -1,7 +1,7 @@
# REQUIRES: asserts
#
# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1\
+# RUN: -window-sched=force -filetype=null 2>&1\
# RUN: | FileCheck %s
# The bug was reported at https://github.com/llvm/llvm-project/issues/123165.
>From 4f103fc9396958febcbd7f97a1d26c7c35ca6c89 Mon Sep 17 00:00:00 2001
From: akiratian <akiratian at tencent.com>
Date: Fri, 17 Jan 2025 16:04:03 +0800
Subject: [PATCH 3/6] [llvm][CodeGen] Modifications made based on review
comments 2
---
llvm/lib/CodeGen/WindowScheduler.cpp | 4 ++--
llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir | 3 +--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 2177afcfab3ea1..a329eaa24dab32 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -303,6 +303,7 @@ void WindowScheduler::generateTripleMBB() {
if (Register AntiReg = getAntiRegister(MI))
DefPairs[MI->getOperand(0).getReg()] = AntiReg;
auto *NewMI = MF->CloneMachineInstr(MI);
+ Context->LIS->RemoveMachineInstrFromMaps(*NewMI);
MBB->push_back(NewMI);
TriMIs.push_back(NewMI);
TriToOri[NewMI] = MI;
@@ -316,6 +317,7 @@ void WindowScheduler::generateTripleMBB() {
(MI->isTerminator() && Cnt < DuplicateNum - 1))
continue;
auto *NewMI = MF->CloneMachineInstr(MI);
+ Context->LIS->RemoveMachineInstrFromMaps(*NewMI);
DenseMap<Register, Register> NewDefs;
// New defines are updated.
for (auto MO : NewMI->all_defs())
@@ -653,8 +655,6 @@ void WindowScheduler::updateLiveIntervals() {
if (!is_contained(UsedRegs, Reg))
UsedRegs.push_back(Reg);
}
- // Remove the residual slot index of newly cloned MI.
- Context->LIS->RemoveMachineInstrFromMaps(MI);
}
Context->LIS->repairIntervalsInRange(MBB, MBB->begin(), MBB->end(), UsedRegs);
}
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir b/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir
index c43fce5707de88..560503ac379233 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-1.mir
@@ -1,8 +1,7 @@
# REQUIRES: asserts
#
# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -filetype=null 2>&1\
-# RUN: | FileCheck %s
+# RUN: -filetype=null 2>&1 | FileCheck %s
# The bug was reported at https://github.com/llvm/llvm-project/issues/123165.
# It is caused by the corruption of live intervals in certain scenarios.
>From f1493200aba0b362a4c38e0265da12a2b27ceaa8 Mon Sep 17 00:00:00 2001
From: akiratian <akiratian at tencent.com>
Date: Fri, 17 Jan 2025 16:16:35 +0800
Subject: [PATCH 4/6] [llvm][CodeGen] Modifications made based on review
comments 3
---
llvm/lib/CodeGen/WindowScheduler.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index a329eaa24dab32..89f7d25b8c0665 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -647,7 +647,7 @@ void WindowScheduler::expand() {
void WindowScheduler::updateLiveIntervals() {
SmallVector<Register, 128> UsedRegs;
- for (MachineInstr &MI : *MBB) {
+ for (MachineInstr &MI : *MBB)
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || MO.getReg() == 0)
continue;
@@ -655,7 +655,6 @@ void WindowScheduler::updateLiveIntervals() {
if (!is_contained(UsedRegs, Reg))
UsedRegs.push_back(Reg);
}
- }
Context->LIS->repairIntervalsInRange(MBB, MBB->begin(), MBB->end(), UsedRegs);
}
>From 4b586c2fe69470838c833afda98f99f1928fa65f Mon Sep 17 00:00:00 2001
From: akiratian <akiratian at tencent.com>
Date: Wed, 22 Jan 2025 10:43:07 +0800
Subject: [PATCH 5/6] [llvm][CodeGen] Modifications made based on review
comments 4
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 2 +-
llvm/lib/CodeGen/ModuloSchedule.cpp | 2 +-
llvm/lib/CodeGen/WindowScheduler.cpp | 4 +---
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 2 +-
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +-
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 7 ++++++-
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 6 +++++-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +-
8 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 165af902e42d08..02e14d6731cc27 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -810,7 +810,7 @@ class TargetInstrInfo : public MCInstrInfo {
///
/// Once this function is called, no other functions on this object are
/// valid; the loop has been removed.
- virtual void disposed() = 0;
+ virtual void disposed(LiveIntervals *LIS = nullptr) = 0;
/// Return true if the target can expand pipelined schedule with modulo
/// variable expansion.
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp
index 414c8cd71809db..d99b6ace01000d 100644
--- a/llvm/lib/CodeGen/ModuloSchedule.cpp
+++ b/llvm/lib/CodeGen/ModuloSchedule.cpp
@@ -899,7 +899,7 @@ void ModuloScheduleExpander::addBranches(MachineBasicBlock &PreheaderBB,
LastEpi->eraseFromParent();
}
if (LastPro == KernelBB) {
- LoopInfo->disposed();
+ LoopInfo->disposed(&LIS);
NewKernel = nullptr;
}
LastPro->clear();
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 89f7d25b8c0665..6bfd3fa7b254f3 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -271,7 +271,7 @@ void WindowScheduler::backupMBB() {
// Remove MIs and the corresponding live intervals.
for (auto &MI : make_early_inc_range(*MBB)) {
Context->LIS->RemoveMachineInstrFromMaps(MI);
- MBB->remove(&MI);
+ MI.removeFromParent();
}
}
@@ -303,7 +303,6 @@ void WindowScheduler::generateTripleMBB() {
if (Register AntiReg = getAntiRegister(MI))
DefPairs[MI->getOperand(0).getReg()] = AntiReg;
auto *NewMI = MF->CloneMachineInstr(MI);
- Context->LIS->RemoveMachineInstrFromMaps(*NewMI);
MBB->push_back(NewMI);
TriMIs.push_back(NewMI);
TriToOri[NewMI] = MI;
@@ -317,7 +316,6 @@ void WindowScheduler::generateTripleMBB() {
(MI->isTerminator() && Cnt < DuplicateNum - 1))
continue;
auto *NewMI = MF->CloneMachineInstr(MI);
- Context->LIS->RemoveMachineInstrFromMaps(*NewMI);
DenseMap<Register, Register> NewDefs;
// New defines are updated.
for (auto MO : NewMI->all_defs())
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index fd24e49f948a20..8a713b73f5eef0 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -10140,7 +10140,7 @@ class AArch64PipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
void adjustTripCount(int TripCountAdjust) override {}
- void disposed() override {}
+ void disposed(LiveIntervals *LIS) override {}
bool isMVEExpanderSupported() override { return true; }
};
} // namespace
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index ae54bad0a05543..6e3252634e4327 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6848,7 +6848,7 @@ class ARMPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
void adjustTripCount(int TripCountAdjust) override {}
- void disposed() override {}
+ void disposed(LiveIntervals *LIS) override {}
};
void ARMPipelinerLoopInfo::bumpCrossIterationPressure(RegPressureTracker &RPT,
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 366ccb0e00fa8e..afe4b0c541160f 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -21,6 +21,7 @@
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/DFAPacketizer.h"
+#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
@@ -795,7 +796,11 @@ class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
Loop->getOperand(1).setReg(NewLoopCount);
}
- void disposed() override { Loop->eraseFromParent(); }
+ void disposed(LiveIntervals *LIS) override {
+ if (LIS)
+ LIS->RemoveMachineInstrFromMaps(*Loop);
+ Loop->eraseFromParent();
+ }
};
} // namespace
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index fa45a7fb7fabe6..9cfbb8157cac5a 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -5694,7 +5694,11 @@ class PPCPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
// so we don't need to generate any thing here.
}
- void disposed() override {
+ void disposed(LiveIntervals *LIS) override {
+ if (LIS) {
+ LIS->RemoveMachineInstrFromMaps(*Loop);
+ LIS->RemoveMachineInstrFromMaps(*LoopCount);
+ }
Loop->eraseFromParent();
// Ensure the loop setup instruction is deleted too.
LoopCount->eraseFromParent();
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 1f7e8d87a11b0c..2c7770b02d3f34 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4279,7 +4279,7 @@ class RISCVPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
void adjustTripCount(int TripCountAdjust) override {}
- void disposed() override {}
+ void disposed(LiveIntervals *LIS) override {}
};
} // namespace
>From 874e76cc9fec8f87c40794e0a76a04447c38abc2 Mon Sep 17 00:00:00 2001
From: akiratian <akiratian at tencent.com>
Date: Wed, 22 Jan 2025 12:20:46 +0800
Subject: [PATCH 6/6] [llvm][CodeGen] Modifications made based on review
comments 5
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 2 +-
llvm/lib/CodeGen/WindowScheduler.cpp | 6 +++---
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 1 -
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 --
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 --
5 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 02e14d6731cc27..68592bd0507a86 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -810,7 +810,7 @@ class TargetInstrInfo : public MCInstrInfo {
///
/// Once this function is called, no other functions on this object are
/// valid; the loop has been removed.
- virtual void disposed(LiveIntervals *LIS = nullptr) = 0;
+ virtual void disposed(LiveIntervals *LIS = nullptr) {}
/// Return true if the target can expand pipelined schedule with modulo
/// variable expansion.
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 6bfd3fa7b254f3..f1658e36ae1e92 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -270,15 +270,15 @@ void WindowScheduler::backupMBB() {
OriMIs.push_back(&MI);
// Remove MIs and the corresponding live intervals.
for (auto &MI : make_early_inc_range(*MBB)) {
- Context->LIS->RemoveMachineInstrFromMaps(MI);
- MI.removeFromParent();
+ Context->LIS->getSlotIndexes()->removeMachineInstrFromMaps(MI, true);
+ MBB->remove(&MI);
}
}
void WindowScheduler::restoreMBB() {
// Erase MIs and the corresponding live intervals.
for (auto &MI : make_early_inc_range(*MBB)) {
- Context->LIS->RemoveMachineInstrFromMaps(MI);
+ Context->LIS->getSlotIndexes()->removeMachineInstrFromMaps(MI, true);
MI.eraseFromParent();
}
// Restore MBB to the state before window scheduling.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 8a713b73f5eef0..f80b1248a527c9 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -10140,7 +10140,6 @@ class AArch64PipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
void adjustTripCount(int TripCountAdjust) override {}
- void disposed(LiveIntervals *LIS) override {}
bool isMVEExpanderSupported() override { return true; }
};
} // namespace
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 6e3252634e4327..eae2f740644342 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6847,8 +6847,6 @@ class ARMPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
void setPreheader(MachineBasicBlock *NewPreheader) override {}
void adjustTripCount(int TripCountAdjust) override {}
-
- void disposed(LiveIntervals *LIS) override {}
};
void ARMPipelinerLoopInfo::bumpCrossIterationPressure(RegPressureTracker &RPT,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 2c7770b02d3f34..77e3aa37d40044 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4278,8 +4278,6 @@ class RISCVPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
void setPreheader(MachineBasicBlock *NewPreheader) override {}
void adjustTripCount(int TripCountAdjust) override {}
-
- void disposed(LiveIntervals *LIS) override {}
};
} // namespace
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