[llvm] [IA][RISCV] Support VP intrinsics in InterleavedAccessPass (PR #120490)

[Min-Yih Hsu via llvm-commits]

mshockwave wrote:

> Thanks for working on this, this will be important for EVL tail folding.
> 
> I noticed though that we don't support factor > 2 [de]interleaves for non-VP scalable loads and stores on RISC-V yet.
> 
> It seems strange that we would support it for VP ops but not for regular ops, could this PR be reworked to maybe add support for the latter first? I.e. consolidating the target-independent BFS here + the AArch64 TLI pattern matching.

I have split the generalized power-of-two (de)interleave support for non-vp load/store into #123863 . I have also updated this PR to reflect the change.

Together, now both AArch64 and RISC-V share the same factor calculation logics that is capable of analyzing any power-of-two (de)interleave intrinsics.

https://github.com/llvm/llvm-project/pull/120490