[llvm] [AMDGPU] Fix unreachable reg bit width (PR #122107)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,15 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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arsenm wrote:

Rename test file 

https://github.com/llvm/llvm-project/pull/122107