[llvm] [AMDGPU] Update AMDGPUUsage.rst to document two intrinsics (PR #123816)
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Tue Jan 21 12:53:44 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jun Wang (jwanggit86)
<details>
<summary>Changes</summary>
The AMDGPUUsage.rst file is updated to document tow intrinsics: llvm.amdgcn.move.dpp and llvm.amdgcn.update.dpp.
---
Full diff: https://github.com/llvm/llvm-project/pull/123816.diff
1 Files Affected:
- (modified) llvm/docs/AMDGPUUsage.rst (+12)
``````````diff
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 40b393224f15dd..132a7444805620 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1422,6 +1422,18 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
Returns a pair for the swapped registers. The first element of the return
corresponds to the swapped element of the first argument.
+ llvm.amdgcn.mov.dpp The llvm.amdgcn.mov.dpp.i32 intrinsic represents the mov.dpp operation in AMDGPU.
+ This operation is being deprecated and can be replaced with llvm.amdgcn.update.dpp.
+
+ llvm.amdgcn.update.dpp The llvm.amdgcn.update.dpp intrinsic represents the update.dpp operation in AMDGPU.
+ It takes an old value, a source operand, a DPP control operand, a row mask, a bank mask, and a bound control.
+ This operation is equivalent to a sequence of v_mov_b32 operations.
+ It is preferred over llvm.amdgcn.mov.dpp.i32 for future use.
+ `llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>`
+ Should be equivalent to:
+ - `v_mov_b32 <dest> <old>`
+ - `v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>`
+
============================================== ==========================================================
.. TODO::
``````````
</details>
https://github.com/llvm/llvm-project/pull/123816
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