[llvm] [LV][EVL] Generate negative strided load/store for reversed load/store (PR #123608)

[Mel Chen via llvm-commits]

https://github.com/Mel-Chen commented:

I am wondering about the necessity of emitting vp.stride_load/store in the vectorizer stage. 
Can we convert load + reverse/ reverse + store to strided load/store in CodeGenPrepare? Similar functionality to RISC-V gather/scatter lowering and Interleaved Access Pass.
https://godbolt.org/z/rc3zPqrez

https://github.com/llvm/llvm-project/pull/123608