[llvm] 0eb7195 - [X86] LowerMUL/LowerRotate - avoid undefs in shuffle mask to prevent premature optimization

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2025-01-21T14:20:38Z
New Revision: 0eb7195d71fff491a6bc6a3a1ad280f3b635d925

URL: https://github.com/llvm/llvm-project/commit/0eb7195d71fff491a6bc6a3a1ad280f3b635d925
DIFF: https://github.com/llvm/llvm-project/commit/0eb7195d71fff491a6bc6a3a1ad280f3b635d925.diff

LOG: [X86] LowerMUL/LowerRotate - avoid undefs in shuffle mask to prevent premature optimization

Later SimplifyDemandedVectorElts calls will simplify any remaining shuffles though the X86ISD::PMULUDQ node.

Avoids regression in #123596

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 87f3f7984989e1..a956074e50d86f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -29215,7 +29215,7 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget &Subtarget,
            "Should not custom lower when pmulld is available!");
 
     // Extract the odd parts.
-    static const int UnpackMask[] = { 1, -1, 3, -1 };
+    static const int UnpackMask[] = {1, 1, 3, 3};
     SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
     SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
 
@@ -31253,7 +31253,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
   // to v2i64 results at a time. The upper 32-bits contain the wrapped bits
   // that can then be OR'd with the lower 32-bits.
   assert(VT == MVT::v4i32 && "Only v4i32 vector rotate expected");
-  static const int OddMask[] = {1, -1, 3, -1};
+  static const int OddMask[] = {1, 1, 3, 3};
   SDValue R13 = DAG.getVectorShuffle(VT, DL, R, R, OddMask);
   SDValue Scale13 = DAG.getVectorShuffle(VT, DL, Scale, Scale, OddMask);