[llvm] [AMDGPU] Fix crash due to missing check for FLAT instructions that dont use vector registers when computing VALU hazard. (PR #123627)

[Matt Arsenault via llvm-commits]

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@@ -858,9 +858,12 @@ int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) {
   }
 
   if (TII->isFLAT(MI)) {
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arsenm wrote:

Is the MIMG case above doing anything? It looks like it's just an assert?  I'm also surprised we're querying the operand before the instruction type 

https://github.com/llvm/llvm-project/pull/123627