[llvm] [AMDGPU][NewPM] Port SILowerWWMCopies to NPM (PR #123695)

[Christudasan Devadasan via llvm-commits]

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@@ -0,0 +1,43 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=liveintervals,virtregmap,si-lower-wwm-copies -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes="require<live-intervals>,require<virtregmap>,si-lower-wwm-copies" -o - %s | FileCheck %s
+
+# Check for two cases of $scc being live and dead.
+---
+name: lower-wwm-copies
+registers:
+  - { id: 1, class: vgpr_32, flags: [ WWM_REG ]}
+machineFunctionInfo:
+  sgprForEXECCopy: '$sgpr2_sgpr3'
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: lower-wwm-copies
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $vgpr0, $scc
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
+  ; CHECK-NEXT:   S_CMP_EQ_U32 [[DEF]], 0, implicit-def $scc
+  ; CHECK-NEXT:   $sgpr2_sgpr3 = S_MOV_B64 killed $exec
+  ; CHECK-NEXT:   $exec = S_MOV_B64 -1
+  ; CHECK-NEXT:   $vgpr1 = COPY $vgpr0
+  ; CHECK-NEXT:   $exec = S_MOV_B64 killed $sgpr2_sgpr3
+  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   liveins: $vgpr1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $sgpr2_sgpr3 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
+  ; CHECK-NEXT:   $vgpr2 = COPY $vgpr1
+  ; CHECK-NEXT:   $exec = S_MOV_B64 killed $sgpr2_sgpr3
+  bb.0:
+    liveins: $vgpr0, $scc
+    %0:sgpr_32 = IMPLICIT_DEF
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cdevadas wrote:

I would have used a physreg for this operand. SGPR allocation is done by now as per the pass flow. It should still work with the SGPR virtual register though.

https://github.com/llvm/llvm-project/pull/123695