[llvm] [X86] Add verifyTargetSDNode for x86 target specific nodes (PR #123589)
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 21 03:34:39 PST 2025
================
@@ -61009,3 +61009,31 @@ Align X86TargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
return Align(1ULL << ExperimentalPrefInnermostLoopAlignment);
return TargetLowering::getPrefLoopAlignment();
}
+
+#ifndef NDEBUG
+void X86TargetLowering::verifyTargetSDNode(const SDNode *N) const {
+ switch (N->getOpcode()) {
+ default:
+ break;
+ case X86ISD::KSHIFTL:
+ case X86ISD::KSHIFTR: {
+ EVT VT = N->getValueType(0);
+ auto *Amt = cast<ConstantSDNode>(N->getOperand(1));
+ assert(Amt->getAPIntValue().ult(VT.getVectorNumElements()) &&
+ "Out of range KSHIFT shift amount");
+ break;
+ }
+ case X86ISD::PSADBW: {
+ EVT VT = N->getValueType(0);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
+ LHS.getValueType() == RHS.getValueType() &&
+ LHS.getValueSizeInBits() == VT.getSizeInBits() &&
+ LHS.getValueType().getScalarType() == MVT::i8 &&
----------------
phoebewang wrote:
We have defined the node with
`SDTCVecEltisVT<0, i64>`, `SDTCVecEltisVT<1, i8>` and `SDTCisSameAs<1,2>`.
Do we still need these check here?
https://github.com/llvm/llvm-project/pull/123589
More information about the llvm-commits
mailing list