[llvm] [BOLT][AArch64] Introduce SPE mode in BasicAggregation (PR #120741)

[Paschalis Mpeis via llvm-commits]

paschalis-mpeis wrote:

Great, thanks a lot Michael for filling in with details!

Indeed the differences are subtle. Just want to clarify that I've answered a slightly different question:
> What I believe you are asking here is to configure SPE to get us a pair of SRC -> TGT , where SRC and TGT are two taken branches. In other words, make SPE act as an LBR-like buffer with a branch stack depth of 1.

Whether we filter-out the non-taken branches at the HW collection level (with the `inv_event_filter` interface) or in post-processing SW, the information loss still holds:
> Please note that if we filter-out any non-taken branches at this point (ie `perf script`), then we'll exclude information we cannot later infer.

And regardless of filtering, we cannot end up with a pair of two taken branches, which could have left opportunities for inferring any FTs in between them.

https://github.com/llvm/llvm-project/pull/120741