[llvm] 7bb363b - [CodeGen] Use MCRegister for ignoreCSRForAllocationOrder. (#123685)

[via llvm-commits]

Author: Craig Topper
Date: 2025-01-21T00:04:57-08:00
New Revision: 7bb363bdd4e87ee0b1ded74ef2616643153ff756

URL: https://github.com/llvm/llvm-project/commit/7bb363bdd4e87ee0b1ded74ef2616643153ff756
DIFF: https://github.com/llvm/llvm-project/commit/7bb363bdd4e87ee0b1ded74ef2616643153ff756.diff

LOG: [CodeGen] Use MCRegister for ignoreCSRForAllocationOrder. (#123685)

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
    llvm/lib/Target/ARM/ARMSubtarget.cpp
    llvm/lib/Target/ARM/ARMSubtarget.h

Removed: 
    


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diff  --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index a94ebf55f6c1ef..76c94981e1afce 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -324,7 +324,7 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
   /// written in the tablegen descriptions, false if it should allocate
   /// the specified physical register later if is it callee-saved.
   virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
-                                           unsigned PhysReg) const {
+                                           MCRegister PhysReg) const {
     return false;
   }
 

diff  --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 07207e29bf7d3a..893084785e6f05 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -478,7 +478,7 @@ unsigned ARMSubtarget::getGPRAllocationOrder(const MachineFunction &MF) const {
 }
 
 bool ARMSubtarget::ignoreCSRForAllocationOrder(const MachineFunction &MF,
-                                               unsigned PhysReg) const {
+                                               MCRegister PhysReg) const {
   // To minimize code size in Thumb2, we prefer the usage of low regs (lower
   // cost per use) so we can  use narrow encoding. By default, caller-saved
   // registers (e.g. lr, r12) are always  allocated first, regardless of

diff  --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 611eeac9ef7128..7329d3f2055f0c 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -523,7 +523,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
   }
 
   bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
-                                   unsigned PhysReg) const override;
+                                   MCRegister PhysReg) const override;
   unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
 };