[llvm] 9d9c561 - [ARM] Use MCRegister instead of unsigned. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 20 19:37:49 PST 2025
Author: Craig Topper
Date: 2025-01-20T19:36:44-08:00
New Revision: 9d9c5619a5156a5be6ee5e5fd45924b26a85626e
URL: https://github.com/llvm/llvm-project/commit/9d9c5619a5156a5be6ee5e5fd45924b26a85626e
DIFF: https://github.com/llvm/llvm-project/commit/9d9c5619a5156a5be6ee5e5fd45924b26a85626e.diff
LOG: [ARM] Use MCRegister instead of unsigned. NFC
Primarily around uses of getSubReg/getSuperReg.
Added:
Modified:
llvm/lib/Target/ARM/A15SDOptimizer.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/lib/Target/ARM/ARMFrameLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
index be87707a297d25..bb9a0a2bdf98b0 100644
--- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp
+++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
@@ -142,9 +142,10 @@ bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
}
unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
- unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
- &ARM::DPRRegClass);
- if (DReg != ARM::NoRegister) return ARM::ssub_1;
+ MCRegister DReg =
+ TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
+ if (DReg)
+ return ARM::ssub_1;
return ARM::ssub_0;
}
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index ae54bad0a05543..2bca2c08c34540 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -825,7 +825,7 @@ unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
- unsigned DestReg, bool KillSrc,
+ MCRegister DestReg, bool KillSrc,
const ARMSubtarget &Subtarget) const {
unsigned Opc = Subtarget.isThumb()
? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
@@ -845,7 +845,7 @@ void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
- unsigned SrcReg, bool KillSrc,
+ MCRegister SrcReg, bool KillSrc,
const ARMSubtarget &Subtarget) const {
unsigned Opc = Subtarget.isThumb()
? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
@@ -1727,10 +1727,10 @@ bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
return false;
const TargetRegisterInfo *TRI = &getRegisterInfo();
- unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
- &ARM::DPRRegClass);
- unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
- &ARM::DPRRegClass);
+ MCRegister DstRegD =
+ TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, &ARM::DPRRegClass);
+ MCRegister SrcRegD =
+ TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, &ARM::DPRRegClass);
if (!DstRegD || !SrcRegD)
return false;
@@ -2594,7 +2594,7 @@ bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
// Now try to find enough space in the reglist to allocate NumBytes.
for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded;
--CurRegEnc) {
- unsigned CurReg = RegClass->getRegister(CurRegEnc);
+ MCRegister CurReg = RegClass->getRegister(CurRegEnc);
if (IsT1PushPop && CurRegEnc > TRI->getEncodingValue(ARM::R7))
continue;
if (!IsPop) {
@@ -5089,13 +5089,14 @@ ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {
return std::make_pair(ExeGeneric, 0);
}
-static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
- unsigned SReg, unsigned &Lane) {
- unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
+static MCRegister getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
+ unsigned SReg, unsigned &Lane) {
+ MCRegister DReg =
+ TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
Lane = 0;
- if (DReg != ARM::NoRegister)
- return DReg;
+ if (DReg)
+ return DReg;
Lane = 1;
DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
@@ -5120,12 +5121,13 @@ static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
/// (including the case where the DPR itself is defined), it should not.
///
static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
- MachineInstr &MI, unsigned DReg,
- unsigned Lane, unsigned &ImplicitSReg) {
+ MachineInstr &MI, MCRegister DReg,
+ unsigned Lane,
+ MCRegister &ImplicitSReg) {
// If the DPR is defined or used already, the other SPR lane will be chained
// correctly, so there is nothing to be done.
if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
- ImplicitSReg = 0;
+ ImplicitSReg = MCRegister();
return true;
}
@@ -5142,13 +5144,14 @@ static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
// If the register is known not to be live, there is no need to add an
// implicit-use.
- ImplicitSReg = 0;
+ ImplicitSReg = MCRegister();
return true;
}
void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
unsigned Domain) const {
- unsigned DstReg, SrcReg, DReg;
+ unsigned DstReg, SrcReg;
+ MCRegister DReg;
unsigned Lane;
MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
const TargetRegisterInfo *TRI = &getRegisterInfo();
@@ -5218,7 +5221,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
- unsigned ImplicitSReg;
+ MCRegister ImplicitSReg;
if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
break;
@@ -5237,7 +5240,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
// The narrower destination must be marked as set to keep previous chains
// in place.
MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
- if (ImplicitSReg != 0)
+ if (ImplicitSReg)
MIB.addReg(ImplicitSReg, RegState::Implicit);
break;
}
@@ -5249,11 +5252,12 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
- unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
+ unsigned DstLane = 0, SrcLane = 0;
+ MCRegister DDst, DSrc;
DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
- unsigned ImplicitSReg;
+ MCRegister ImplicitSReg;
if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
break;
@@ -5273,7 +5277,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
// more, so add them in manually.
MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
MIB.addReg(SrcReg, RegState::Implicit);
- if (ImplicitSReg != 0)
+ if (ImplicitSReg)
MIB.addReg(ImplicitSReg, RegState::Implicit);
break;
}
@@ -5297,7 +5301,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
// On the first instruction, both DSrc and DDst may be undef if present.
// Specifically when the original instruction didn't have them as an
// <imp-use>.
- unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
+ MCRegister CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
bool CurUndef = !MI.readsRegister(CurReg, TRI);
NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
@@ -5402,8 +5406,8 @@ unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
return 0;
} else if (ARM::SPRRegClass.contains(Reg)) {
// Physical register: MI must define the full D-reg.
- unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
- &ARM::DPRRegClass);
+ MCRegister DReg =
+ TRI->getMatchingSuperReg(Reg, ARM::ssub_0, &ARM::DPRRegClass);
if (!DReg || !MI.definesRegister(DReg, TRI))
return 0;
}
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index b6f20e6f99a0a9..9422e12c5dfc51 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -201,10 +201,10 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
int &FrameIndex) const override;
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned SrcReg, bool KillSrc,
+ MCRegister SrcReg, bool KillSrc,
const ARMSubtarget &Subtarget) const;
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, bool KillSrc,
+ MCRegister DestReg, bool KillSrc,
const ARMSubtarget &Subtarget) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 291bfc0610f85d..22ebe175ff62fc 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -334,12 +334,12 @@ ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
}
// Get the other register in a GPRPair.
-static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd,
- const MCRegisterInfo *RI) {
+static MCRegister getPairedGPR(MCRegister Reg, bool Odd,
+ const MCRegisterInfo *RI) {
for (MCPhysReg Super : RI->superregs(Reg))
if (ARM::GPRPairRegClass.contains(Super))
return RI->getSubReg(Super, Odd ? ARM::gsub_1 : ARM::gsub_0);
- return 0;
+ return MCRegister();
}
// Resolve the RegPairEven / RegPairOdd register allocator hints.
@@ -390,7 +390,7 @@ bool ARMBaseRegisterInfo::getRegAllocationHints(
if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
continue;
// Don't provide hints that are paired to a reserved register.
- MCPhysReg Paired = getPairedGPR(Reg, !Odd, this);
+ MCRegister Paired = getPairedGPR(Reg, !Odd, this);
if (!Paired || MRI.isReserved(Paired))
continue;
Hints.push_back(Reg);
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
index 478c32fa724ffc..68a28043fd32ec 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -41,7 +41,7 @@ namespace ARMRI {
} // end namespace ARMRI
-static inline bool isCalleeSavedRegister(unsigned Reg,
+static inline bool isCalleeSavedRegister(MCRegister Reg,
const MCPhysReg *CSRegs) {
for (unsigned i = 0; CSRegs[i]; ++i)
if (Reg == CSRegs[i])
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 2e5dc09c00ce62..9e1f3fcbdc43f4 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -516,8 +516,8 @@ static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
/// corresponding to the specified register spacing. Not all of the results
/// are necessarily valid, e.g., a Q register only has 2 D subregisters.
static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
- const TargetRegisterInfo *TRI, unsigned &D0,
- unsigned &D1, unsigned &D2, unsigned &D3) {
+ const TargetRegisterInfo *TRI, MCRegister &D0,
+ MCRegister &D1, MCRegister &D2, MCRegister &D3) {
if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
D0 = TRI->getSubReg(Reg, ARM::dsub_0);
D1 = TRI->getSubReg(Reg, ARM::dsub_1);
@@ -585,11 +585,11 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
SubRegIndex = ARM::dsub_1;
}
Register SubReg = TRI->getSubReg(DstReg, SubRegIndex);
- unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
- &ARM::DPairSpcRegClass);
+ MCRegister DstRegPair =
+ TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, &ARM::DPairSpcRegClass);
MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
} else {
- unsigned D0, D1, D2, D3;
+ MCRegister D0, D1, D2, D3;
GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
if (NumRegs > 1 && TableEntry->copyAllListRegs)
@@ -715,7 +715,7 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
bool SrcIsKill = MI.getOperand(OpIdx).isKill();
bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
Register SrcReg = MI.getOperand(OpIdx++).getReg();
- unsigned D0, D1, D2, D3;
+ MCRegister D0, D1, D2, D3;
GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
MIB.addReg(D0, getUndefRegState(SrcIsUndef));
if (NumRegs > 1 && TableEntry->copyAllListRegs)
@@ -769,7 +769,7 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
}
assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
- unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
+ MCRegister D0, D1, D2, D3;
unsigned DstReg = 0;
bool DstIsDead = false;
if (TableEntry->IsLoad) {
@@ -851,7 +851,7 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
bool SrcIsKill = MI.getOperand(OpIdx).isKill();
Register SrcReg = MI.getOperand(OpIdx++).getReg();
- unsigned D0, D1, D2, D3;
+ MCRegister D0, D1, D2, D3;
GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
MIB.addReg(D0);
@@ -1547,7 +1547,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
} else {
// For big-endian targets we need to load the two subregisters of Reg
// manually because VLDRD would load them in wrong order
- unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0);
+ MCRegister SReg0 = TRI->getSubReg(Reg, ARM::ssub_0);
BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0)
.addReg(ARM::SP)
.addImm((Reg - ARM::D0) * 2)
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 8b94bfac9b0c0d..3393c55f1639d5 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -1917,8 +1917,8 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
// 16-byte aligned vst1.64 with 4 d-regs and address writeback.
// The writeback is only needed when emitting two vst1.64 instructions.
if (NumAlignedDPRCS2Regs >= 6) {
- unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
- &ARM::QQPRRegClass);
+ MCRegister SupReg =
+ TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);
MBB.addLiveIn(SupReg);
BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
.addReg(ARM::R4, RegState::Kill)
@@ -1936,8 +1936,8 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
// 16-byte aligned vst1.64 with 4 d-regs, no writeback.
if (NumAlignedDPRCS2Regs >= 4) {
- unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
- &ARM::QQPRRegClass);
+ MCRegister SupReg =
+ TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);
MBB.addLiveIn(SupReg);
BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
.addReg(ARM::R4)
@@ -1951,8 +1951,8 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
// 16-byte aligned vst1.64 with 2 d-regs.
if (NumAlignedDPRCS2Regs >= 2) {
- unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
- &ARM::QPRRegClass);
+ MCRegister SupReg =
+ TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QPRRegClass);
MBB.addLiveIn(SupReg);
BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
.addReg(ARM::R4)
@@ -2049,8 +2049,8 @@ static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
// 16-byte aligned vld1.64 with 4 d-regs and writeback.
if (NumAlignedDPRCS2Regs >= 6) {
- unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
- &ARM::QQPRRegClass);
+ MCRegister SupReg =
+ TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);
BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
.addReg(ARM::R4, RegState::Define)
.addReg(ARM::R4, RegState::Kill)
@@ -2067,8 +2067,8 @@ static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
// 16-byte aligned vld1.64 with 4 d-regs, no writeback.
if (NumAlignedDPRCS2Regs >= 4) {
- unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
- &ARM::QQPRRegClass);
+ MCRegister SupReg =
+ TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);
BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
.addReg(ARM::R4)
.addImm(16)
@@ -2080,8 +2080,8 @@ static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
// 16-byte aligned vld1.64 with 2 d-regs.
if (NumAlignedDPRCS2Regs >= 2) {
- unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
- &ARM::QPRRegClass);
+ MCRegister SupReg =
+ TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QPRRegClass);
BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
.addReg(ARM::R4)
.addImm(16)
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