[llvm] [VectorCombine] Allow shuffling between vectors the same type but different element sizes (PR #121216)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 20 11:08:45 PST 2025
================
@@ -3067,42 +3067,69 @@ bool VectorCombine::foldInsExtVectorToShuffle(Instruction &I) {
m_ConstantInt(InsIdx))))
return false;
- auto *VecTy = dyn_cast<FixedVectorType>(I.getType());
- if (!VecTy || SrcVec->getType() != VecTy)
+ auto *DstVecTy = dyn_cast<FixedVectorType>(I.getType());
+ auto *SrcVecTy = dyn_cast<FixedVectorType>(SrcVec->getType());
+ // We can try combining vectors with different element sizes.
+ if (!DstVecTy || !SrcVecTy ||
+ SrcVecTy->getElementType() != DstVecTy->getElementType())
return false;
- unsigned NumElts = VecTy->getNumElements();
- if (ExtIdx >= NumElts || InsIdx >= NumElts)
+ unsigned NumDstElts = DstVecTy->getNumElements();
+ unsigned NumSrcElts = SrcVecTy->getNumElements();
+ if (InsIdx >= NumDstElts || ExtIdx >= NumSrcElts || NumDstElts == 1)
return false;
// Insertion into poison is a cheaper single operand shuffle.
TargetTransformInfo::ShuffleKind SK;
- SmallVector<int> Mask(NumElts, PoisonMaskElem);
- if (isa<PoisonValue>(DstVec) && !isa<UndefValue>(SrcVec)) {
+ SmallVector<int> Mask(NumDstElts, PoisonMaskElem);
+
+ bool NeedExpOrNarrow = NumSrcElts != NumDstElts;
+ bool NeedDstSrcSwap = isa<PoisonValue>(DstVec) && !isa<UndefValue>(SrcVec);
+ if (NeedDstSrcSwap) {
SK = TargetTransformInfo::SK_PermuteSingleSrc;
- Mask[InsIdx] = ExtIdx;
+ if (!NeedExpOrNarrow)
+ Mask[InsIdx] = ExtIdx;
+ else
+ Mask[InsIdx] = 0;
----------------
ParkHanbum wrote:
sorry but I can't understand where can be use a `SK_Select`. when I changed `TargetTransformInfo::SK_PermuteTwoSrc` to `SK = TargetTransformInfo::SK_Select` there is a lot of changed appear include PhaseOrdering/X86/hadd.ll
https://github.com/llvm/llvm-project/pull/121216
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