[llvm] [AArch64][SDAG] Detect non-zeroes in truncating buildvectors in fshl lowering (PR #123597)

[David Green via llvm-commits]

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@@ -382,16 +382,16 @@ bool ISD::matchUnaryPredicateImpl(SDValue Op,
     }
 
     auto *Cst = dyn_cast<ConstNodeType>(Op.getOperand(i));
-    if (!Cst || Cst->getValueType(0) != SVT || !Match(Cst))
+    if (!Cst || (!AllowTrunc && Cst->getValueType(0) != SVT) || !Match(Cst))
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davemgreen wrote:

AFAIU there are checks in VerifySDNode the check the operands are >= the size of the scalar type, so I think this should always be true. Let me know if it would be better still test it or to add another assert here.

https://github.com/llvm/llvm-project/pull/123597