[llvm] [GISel] Fold shifts to constant result. (PR #123510)

[Matt Arsenault via llvm-commits]

================
@@ -0,0 +1,115 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            combine_ashr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr31
+
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: combine_ashr
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))
+    ; CHECK-NEXT: SI_RETURN
+    %9:_(s32) = COPY $vgpr0
+    %10:_(s32) = COPY $vgpr1
+    %0:_(p0) = G_MERGE_VALUES %9(s32), %10(s32)
+    %12:_(s32) = G_CONSTANT i32 10
+    %11:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
+    %13:_(s32) = G_ASHR %11, %12(s32)
+    G_STORE %13(s32), %0(p0) :: (store (s32))
+    SI_RETURN
+
+...
+---
+name:            combine_lshr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr31
+
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: combine_lshr
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))
+    ; CHECK-NEXT: SI_RETURN
+    %9:_(s32) = COPY $vgpr0
+    %10:_(s32) = COPY $vgpr1
+    %0:_(p0) = G_MERGE_VALUES %9(s32), %10(s32)
+    %12:_(s32) = G_CONSTANT i32 10
+    %11:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
+    %13:_(s32) = G_LSHR %11, %12(s32)
+    G_STORE %13(s32), %0(p0) :: (store (s32))
+    SI_RETURN
+
+...
+---
+name:            combine_shl
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr31
+
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: combine_shl
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))
+    ; CHECK-NEXT: SI_RETURN
+    %9:_(s32) = COPY $vgpr0
+    %10:_(s32) = COPY $vgpr1
+    %0:_(p0) = G_MERGE_VALUES %9(s32), %10(s32)
+    %12:_(s32) = G_CONSTANT i32 16
+    %11:_(s32) = G_CONSTANT i32 4294901760
+    %13:_(s32) = G_SHL %11, %12(s32)
+    G_STORE %13(s32), %0(p0) :: (store (s32))
+    SI_RETURN
+
+...
+---
+name:            combine_ashr2
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr31
+
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: combine_ashr2
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
+    ; CHECK-NEXT: G_STORE [[C]](s8), [[MV]](p0) :: (store (s8))
+    ; CHECK-NEXT: SI_RETURN
+    %9:_(s32) = COPY $vgpr0
+    %10:_(s32) = COPY $vgpr1
+    %0:_(p0) = G_MERGE_VALUES %9(s32), %10(s32)
+    %12:_(s32) = G_CONSTANT i32 1
+    %11:_(s8) = G_CONSTANT i8 -2
+    %13:_(s8) = G_ASHR %11, %12(s32)
+    G_STORE %13(s8), %0(p0) :: (store (s8))
+    SI_RETURN
+
+...
----------------
arsenm wrote:

Test vector cases 

https://github.com/llvm/llvm-project/pull/123510