[llvm] [X86] Add verifyTargetSDNode for x86 target specific nodes (PR #123589)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/123589

This allows us to verify/assert the node's validity on creation instead of waiting for when its used in a combine/analysis.

Added some initial verification for X86ISD::KSHIFL\R and X86ISD::PSADBW types - more to follow.

>From 8b4e7e516b13fac254bdad0fe9f6363ab963436c Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Mon, 20 Jan 2025 11:18:56 +0000
Subject: [PATCH] [X86] Add verifyTargetSDNode for x86 target specific nodes

This allows us to verify/assert the node's validity on creation instead of waiting for when its used in a combine/analysis.

Add some initial verification for X86ISD::KSHIFL\R and X86ISD::PSADBW types - more to follow.
---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 28 +++++++++++++++++++++++++
 llvm/lib/Target/X86/X86ISelLowering.h   |  4 ++++
 2 files changed, 32 insertions(+)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 33ddcb57e9b08b..8a4844bc0afce8 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -61009,3 +61009,31 @@ Align X86TargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
     return Align(1ULL << ExperimentalPrefInnermostLoopAlignment);
   return TargetLowering::getPrefLoopAlignment();
 }
+
+#ifndef NDEBUG
+void X86TargetLowering::verifyTargetSDNode(const SDNode *N) const {
+  switch (N->getOpcode()) {
+  default:
+    break;
+  case X86ISD::KSHIFTL:
+  case X86ISD::KSHIFTR: {
+    EVT VT = N->getValueType(0);
+    auto *Amt = cast<ConstantSDNode>(N->getOperand(1));
+    assert(Amt->getAPIntValue().ult(VT.getVectorNumElements()) &&
+           "Out of range KSHIFT shift amount");
+    break;
+  }
+  case X86ISD::PSADBW: {
+    EVT VT = N->getValueType(0);
+    SDValue LHS = N->getOperand(0);
+    SDValue RHS = N->getOperand(1);
+    assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
+           LHS.getValueType() == RHS.getValueType() &&
+           LHS.getValueSizeInBits() == VT.getSizeInBits() &&
+           LHS.getValueType().getScalarType() == MVT::i8 &&
+           "Unexpected PSADBW types");
+    break;
+  }
+  }
+}
+#endif
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 03f10a3c83e30c..b8517018067d8b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1658,6 +1658,10 @@ namespace llvm {
       return TargetLoweringBase::getTypeToTransformTo(Context, VT);
     }
 
+#ifndef NDEBUG
+    void verifyTargetSDNode(const SDNode *N) const override;
+#endif
+
   protected:
     std::pair<const TargetRegisterClass *, uint8_t>
     findRepresentativeClass(const TargetRegisterInfo *TRI,