[llvm] [AMDGPU] Update entry point name for PAL metadata (PR #123581)
David Stuttard via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 20 02:50:02 PST 2025
https://github.com/dstutt created https://github.com/llvm/llvm-project/pull/123581
Old entry-point metadata being updated. Nothing is required
to account for deprecation as nothing uses the old style
>From 6076a48ce6ac0536048fa9d95a3955446b4627fe Mon Sep 17 00:00:00 2001
From: David Stuttard <david.stuttard at amd.com>
Date: Mon, 9 Dec 2024 10:24:20 +0000
Subject: [PATCH] [AMDGPU] Update entry point name for PAL metadata
Old entry-point metadata being updated. Nothing is required
to account for deprecation as nothing uses the old style
---
llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp | 2 +-
llvm/test/CodeGen/AMDGPU/amdpal-cs.ll | 2 +-
llvm/test/CodeGen/AMDGPU/amdpal-es.ll | 2 +-
llvm/test/CodeGen/AMDGPU/amdpal-gs.ll | 2 +-
llvm/test/CodeGen/AMDGPU/amdpal-hs.ll | 2 +-
llvm/test/CodeGen/AMDGPU/amdpal-ls.ll | 2 +-
llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll | 2 +-
llvm/test/CodeGen/AMDGPU/amdpal-vs.ll | 2 +-
llvm/test/CodeGen/AMDGPU/amdpal.ll | 2 +-
llvm/test/CodeGen/AMDGPU/elf-notes.ll | 2 +-
llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll | 8 ++++----
llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll | 2 +-
12 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
index 4ad26ee895c7dd..81aaee0b503bc7 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
@@ -232,7 +232,7 @@ void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
if (isLegacy())
return;
// Msgpack format.
- getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
+ getHwStage(CC)[".entry_point_symbol"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
}
// Set the number of used vgprs in the metadata. This is an optional
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
index a3fd2a942bc2b6..0818f607da0a5c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
@@ -8,7 +8,7 @@
; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .cs:
-; GCN-NEXT: .entry_point: cs_amdpal
+; GCN-NEXT: .entry_point_symbol: cs_amdpal
; GCN-NEXT: .scratch_memory_size: 0
; GCN: .registers:
; GCN-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)':
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-es.ll b/llvm/test/CodeGen/AMDGPU/amdpal-es.ll
index 657fe80be04daf..e37d22c7df372d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-es.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-es.ll
@@ -7,7 +7,7 @@
; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .es:
-; GCN-NEXT: .entry_point: es_amdpal
+; GCN-NEXT: .entry_point_symbol: es_amdpal
; GCN-NEXT: .scratch_memory_size: 0
; GCN: .registers:
; GCN-NEXT: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
index 9f5eb3927c4892..d847f75a5c0939 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
@@ -8,7 +8,7 @@
; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .gs:
-; GCN-NEXT: .entry_point: gs_amdpal
+; GCN-NEXT: .entry_point_symbol: gs_amdpal
; GCN-NEXT: .scratch_memory_size: 0
; GCN: .registers:
; GCN-NEXT: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
index 7eacedf44d09d5..74f5f440c99d79 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
@@ -8,7 +8,7 @@
; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .hs:
-; GCN-NEXT: .entry_point: hs_amdpal
+; GCN-NEXT: .entry_point_symbol: hs_amdpal
; GCN-NEXT: .scratch_memory_size: 0
; GCN: .registers:
; GCN-NEXT: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll b/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
index 973eb561a9a3d0..287cc1201a3c58 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
@@ -7,7 +7,7 @@
; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .ls:
-; GCN-NEXT: .entry_point: ls_amdpal
+; GCN-NEXT: .entry_point_symbol: ls_amdpal
; GCN-NEXT: .scratch_memory_size: 0
; GCN: .registers:
; GCN-NEXT: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll b/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
index ace21207a7eba5..e1767182c359df 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
@@ -11,7 +11,7 @@
; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .ps:
-; GCN-NEXT: .entry_point: amdpal_psenable
+; GCN-NEXT: .entry_point_symbol: amdpal_psenable
; GCN-NEXT: .scratch_memory_size: 0
; GCN: .registers:
; GCN-NEXT: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)':
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
index e554bb8980cecb..b225d978601ab8 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
@@ -8,7 +8,7 @@
; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .vs:
-; GCN-NEXT: .entry_point: vs_amdpal
+; GCN-NEXT: .entry_point_symbol: vs_amdpal
; GCN-NEXT: .scratch_memory_size: 0
; GCN: .registers:
; GCN-NEXT: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal.ll b/llvm/test/CodeGen/AMDGPU/amdpal.ll
index 0ec5aeb24b4235..97fcf0606b5b78 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal.ll
@@ -86,7 +86,7 @@ declare void @llvm.amdgcn.raw.ptr.buffer.store.f32(float, ptr addrspace(8), i32,
; PAL-NEXT: amdpal.pipelines:
; PAL-NEXT: - .hardware_stages:
; PAL-NEXT: .cs:
-; PAL-NEXT: .entry_point: scratch2_cs
+; PAL-NEXT: .entry_point_symbol: scratch2_cs
; PAL-NEXT: .scratch_memory_size: 0x10
; PAL-NEXT: .sgpr_count: 0x
; PAL-NEXT: .vgpr_count: 0x
diff --git a/llvm/test/CodeGen/AMDGPU/elf-notes.ll b/llvm/test/CodeGen/AMDGPU/elf-notes.ll
index 554cb140f42923..e91bed464136f8 100644
--- a/llvm/test/CodeGen/AMDGPU/elf-notes.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf-notes.ll
@@ -66,7 +66,7 @@
; OSABI-PAL-ELF: amdpal.pipelines:
; OSABI-PAL-ELF: - .hardware_stages:
; OSABI-PAL-ELF: .cs:
-; OSABI-PAL-ELF: .entry_point: elf_notes
+; OSABI-PAL-ELF: .entry_point_symbol: elf_notes
; OSABI-PAL-ELF: .scratch_memory_size: 0
; OSABI-PAL-ELF: .sgpr_count: 96
; OSABI-PAL-ELF: .vgpr_count: 1
diff --git a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
index a2baa56ea0c989..f89341d539a0f6 100644
--- a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
+++ b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
@@ -53,7 +53,7 @@
; CHECK-NEXT: .cs:
; CHECK-NEXT: .checksum_value: 0x9444d7d0
; CHECK-NEXT: .debug_mode: false
-; CHECK-NEXT: .entry_point: _amdgpu_cs_main
+; CHECK-NEXT: .entry_point_symbol: _amdgpu_cs_main
; CHECK-NEXT: .excp_en: 0
; CHECK-NEXT: .float_mode: 0xc0
; CHECK-NEXT: .ieee_mode: false
@@ -109,7 +109,7 @@
; CHECK-NEXT: .wgp_mode: false
; CHECK-NEXT: .gs:
; CHECK-NEXT: .debug_mode: false
-; CHECK-NEXT: .entry_point: gs_shader
+; CHECK-NEXT: .entry_point_symbol: gs_shader
; CHECK-NEXT: .ieee_mode: false
; CHECK-NEXT: .lds_size: 0x200
; CHECK-NEXT: .mem_ordered: true
@@ -120,7 +120,7 @@
; CHECK-NEXT: .wgp_mode: true
; CHECK-NEXT: .hs:
; CHECK-NEXT: .debug_mode: false
-; CHECK-NEXT: .entry_point: hs_shader
+; CHECK-NEXT: .entry_point_symbol: hs_shader
; CHECK-NEXT: .ieee_mode: false
; CHECK-NEXT: .lds_size: 0x1000
; CHECK-NEXT: .mem_ordered: true
@@ -131,7 +131,7 @@
; CHECK-NEXT: .wgp_mode: true
; CHECK-NEXT: .ps:
; CHECK-NEXT: .debug_mode: false
-; CHECK-NEXT: .entry_point: ps_shader
+; CHECK-NEXT: .entry_point_symbol: ps_shader
; CHECK-NEXT: .ieee_mode: false
; CHECK-NEXT: .lds_size: 0
; CHECK-NEXT: .mem_ordered: true
diff --git a/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll b/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
index 29520cb7468c7c..e3a6240aac0057 100644
--- a/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
@@ -12,7 +12,7 @@
; GCN-NEXT: amdpal.pipelines:
; GCN-NEXT: - .hardware_stages:
; GCN-NEXT: .cs:
-; GCN-NEXT: .entry_point: _amdgpu_cs_main
+; GCN-NEXT: .entry_point_symbol: _amdgpu_cs_main
; GCN-NEXT: .scratch_memory_size: 0
; SI-NEXT: .sgpr_count: 0x11
; VI-NEXT: .sgpr_count: 0x60
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