[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[James Chesterman via llvm-commits]

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@@ -2046,11 +2057,18 @@ bool AArch64TargetLowering::shouldExpandPartialReductionIntrinsic(
     return true;
 
   EVT VT = EVT::getEVT(I->getType());
-  auto Op1 = I->getOperand(1);
-  EVT Op1VT = EVT::getEVT(Op1->getType());
-  if (Op1VT.getVectorElementType() == VT.getVectorElementType() &&
-      (VT.getVectorElementCount() * 4 == Op1VT.getVectorElementCount() ||
-       VT.getVectorElementCount() * 2 == Op1VT.getVectorElementCount()))
+  auto Input = I->getOperand(1);
+  EVT InputVT = EVT::getEVT(Input->getType());
+
+  if ((InputVT == MVT::nxv4i64 && VT == MVT::nxv2i64) ||
+      (InputVT == MVT::nxv8i32 && VT == MVT::nxv4i32) ||
+      (InputVT == MVT::nxv16i16 && VT == MVT::nxv8i16) ||
+      (InputVT == MVT::nxv16i64 && VT == MVT::nxv4i64) ||
+      (InputVT == MVT::nxv16i32 && VT == MVT::nxv4i32) ||
+      (InputVT == MVT::nxv8i64 && VT == MVT::nxv2i64) ||
+      (InputVT == MVT::v16i64 && VT == MVT::v4i64) ||
+      (InputVT == MVT::v16i32 && VT == MVT::v4i32) ||
+      (InputVT == MVT::v8i32 && VT == MVT::v2i32))
----------------
JamesChesterman wrote:

The removed code would allow types that could be used but would just need to go through legalisation first. Originally, and on the current upstream main branch, at the end of the DAG combine it would return `DAG.expandPartialReduceAdd` (it's `DAG.getPartialReduceAdd` on upstream main). This meant that any types that weren't legal would just end up going to this function. However, when changing the end of the DAG combine to return `SDValue()` instead, these cases would try to go to legalisation, where currently there is not a case for partial reduction ISD nodes.

For now, I've just changed it back to returning the expand function at the end of the DAG combine. When I add legalisation, I'll do the type checking during the DAG combine instead of here.

https://github.com/llvm/llvm-project/pull/117185