[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[James Chesterman via llvm-commits]

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@@ -1451,6 +1451,13 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // Nodes used to represent a partial reduction addition operation (signed and
+  // unsigned).
+  // Operands: Accumulator, Input
+  // Outputs: Output
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JamesChesterman wrote:

Done, specified what needs to be passed into the node as its arguments. It will be similar to what is specified for the intrinsic itself, so `%a` and`%b` need to have the same element type as `%acc`.

https://github.com/llvm/llvm-project/pull/117185