[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[James Chesterman via llvm-commits]

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@@ -8135,15 +8135,19 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
     return;
   }
   case Intrinsic::experimental_vector_partial_reduce_add: {
+    SDLoc dl = getCurSDLoc();
+    SDValue Acc = getValue(I.getOperand(0));
+    EVT AccVT = Acc.getValueType();
+    SDValue Input = getValue(I.getOperand(1));
 
     if (!TLI.shouldExpandPartialReductionIntrinsic(cast<IntrinsicInst>(&I))) {
-      visitTargetIntrinsic(I, Intrinsic);
+      setValue(&I, DAG.getNode(ISD::PARTIAL_REDUCE_UMLA, dl, AccVT, Acc, Input,
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JamesChesterman wrote:

Yes this is arbitrarily chosen. The node is then changed to its correct signedness in the DAG combine. Added a comment explaining this and asserts for the operand types.

https://github.com/llvm/llvm-project/pull/117185