[llvm] [MIPS] [MSA] Widen v2i8, v216 and v2i32 vectors (PR #123040)

[Cinhi Young via llvm-commits]

================
@@ -59,6 +60,29 @@ static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
                                             "stores to their single precision "
                                             "counterparts"));
 
+// Widen the v2 vectors to the register width, i.e. v2i16 -> v8i16,
+// v2i32 -> v4i32, etc, to ensure the correct rail size is used, i.e.
+// INST.h for v16, INST.w for v32, INST.d for v64.
+TargetLoweringBase::LegalizeTypeAction
+MipsSETargetLowering::getPreferredVectorAction(MVT VT) const {
+  if (this->Subtarget.hasMSA() && this->Subtarget.isGP64bit()) {
----------------
Cyanoxygen wrote:

Not required, will lift this check. The calling convention test may change significantly (just like this one), however.

https://github.com/llvm/llvm-project/pull/123040