[llvm] 0e4a10d - [MC] Add MCRegister::isPhysical. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-01-18T22:28:37-08:00
New Revision: 0e4a10dff8eac9ac38d7dbed0c0d32d4a68a5a69

URL: https://github.com/llvm/llvm-project/commit/0e4a10dff8eac9ac38d7dbed0c0d32d4a68a5a69
DIFF: https://github.com/llvm/llvm-project/commit/0e4a10dff8eac9ac38d7dbed0c0d32d4a68a5a69.diff

LOG: [MC] Add MCRegister::isPhysical. NFC

Added: 
    

Modified: 
    llvm/include/llvm/MC/MCRegister.h
    llvm/include/llvm/MC/MCRegisterInfo.h
    llvm/utils/TableGen/AsmMatcherEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/MC/MCRegister.h b/llvm/include/llvm/MC/MCRegister.h
index 2d21e0acca357d..53005bb03c2eea 100644
--- a/llvm/include/llvm/MC/MCRegister.h
+++ b/llvm/include/llvm/MC/MCRegister.h
@@ -68,6 +68,10 @@ class MCRegister {
     return FirstPhysicalReg <= Reg && Reg < FirstStackSlot;
   }
 
+  /// Return true if the specified register number is in the physical register
+  /// namespace.
+  constexpr bool isPhysical() const { return isPhysicalRegister(Reg); }
+
   constexpr operator unsigned() const { return Reg; }
 
   /// Check the provided unsigned value is a valid MCRegister.

diff  --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 164ef1ef44bbba..1579ecb035c21b 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -530,7 +530,7 @@ class MCSubRegIterator
 
   MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
                    bool IncludeSelf = false) {
-    assert(MCRegister::isPhysicalRegister(Reg.id()));
+    assert(Reg.isPhysical());
     I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SubRegs);
     // Initially, the iterator points to Reg itself.
     Val = MCPhysReg(*I);
@@ -600,7 +600,7 @@ class MCSuperRegIterator
 
   MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
                      bool IncludeSelf = false) {
-    assert(MCRegister::isPhysicalRegister(Reg.id()));
+    assert(Reg.isPhysical());
     I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
     // Initially, the iterator points to Reg itself.
     Val = MCPhysReg(*I);
@@ -646,8 +646,7 @@ class MCRegUnitIterator
   MCRegUnitIterator() = default;
 
   MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) {
-    assert(Reg && "Null register has no regunits");
-    assert(MCRegister::isPhysicalRegister(Reg.id()));
+    assert(Reg.isPhysical());
     // Decode the RegUnits MCRegisterDesc field.
     unsigned RU = MCRI->get(Reg).RegUnits;
     unsigned FirstRU = RU & ((1u << RegUnitBits) - 1);

diff  --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 139b1f9d897fa1..7684387d80fe24 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -2522,9 +2522,9 @@ static void emitValidateOperandClass(const CodeGenTarget &Target,
   for (auto &MatchClassName : Table)
     OS << "      " << MatchClassName << ",\n";
   OS << "    };\n\n";
-  OS << "    unsigned RegID = Operand.getReg().id();\n";
-  OS << "    MatchClassKind OpKind = MCRegister::isPhysicalRegister(RegID) ? "
-        "(MatchClassKind)Table[RegID] : InvalidMatchClass;\n";
+  OS << "    MCRegister Reg = Operand.getReg();\n";
+  OS << "    MatchClassKind OpKind = Reg.isPhysical() ? "
+        "(MatchClassKind)Table[Reg.id()] : InvalidMatchClass;\n";
   OS << "    return isSubclass(OpKind, Kind) ? "
      << "(unsigned)MCTargetAsmParser::Match_Success :\n                     "
      << "                 getDiagKindFromRegisterClass(Kind);\n  }\n\n";