[llvm] [RISCV] Select Zvkb VANDN for shorter constant loading sequences (PR #123345)

[Craig Topper via llvm-commits]

topperc wrote:

> I understand this will also need an update in `RISCVDAGToDAGISel::selectInvLogicImm` to allow splat vector uses, but gdb shows it doesn't even enter this function, so my TableGen pattern must be wrong, but I don't know why. Please help.

The RISCVDAGToDAGISel::selectInvLogicImm is getting executed when I tried to test it.

It failed this check

```
  for (const SDNode *U : N->users()) {                                           
    if (!ISD::isBitwiseLogicOp(U->getOpcode()))                                  
      return false;                                                              
  }  
```

https://github.com/llvm/llvm-project/pull/123345