[llvm] b1bf95c - ReduxWidth check for 0 (#123257)
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Fri Jan 17 12:57:04 PST 2025
Author: George Chaltas
Date: 2025-01-17T15:56:58-05:00
New Revision: b1bf95c081297305b2c9810ff04a9dac7216b434
URL: https://github.com/llvm/llvm-project/commit/b1bf95c081297305b2c9810ff04a9dac7216b434
DIFF: https://github.com/llvm/llvm-project/commit/b1bf95c081297305b2c9810ff04a9dac7216b434.diff
LOG: ReduxWidth check for 0 (#123257)
Added assert to check for underflow of ReduxWidth
modified: llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Source code analysis flagged the operation (ReduxWwidth - 1) as
potential underflow, since ReduxWidth is unsigned.
Realize that this should never happen if everything is working right,
but added an assert to check for it just in case.
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 0bf01a8c680bfd..40dd0d4cc4ef68 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -20095,6 +20095,7 @@ class HorizontalReduction {
NumRegs =
TTI.getNumberOfRegisters(TTI.getRegisterClassForType(true, Tp));
while (NumParts > NumRegs) {
+ assert(ReduxWidth > 0 && "ReduxWidth is unexpectedly 0.");
ReduxWidth = bit_floor(ReduxWidth - 1);
VectorType *Tp = getWidenedType(ScalarTy, ReduxWidth);
NumParts = TTI.getNumberOfParts(Tp);
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