[llvm] [X86] Allow speculative BSR/BSF instructions on targets with CMOV (PR #102885)

[via llvm-commits]

comex wrote:

@RKSimon As of (at latest) the October 2024 version of the "Intel® 64 and IA-32 Architectures Software Developer’s Manual", it seems like Intel has done so.  BSR and BSF are both documented as follows:

> If the content of the source operand is zero, the destination operand is unmodified.¹

> 1. On some older processors, use of a 32-bit operand size may clear the upper 32 bits of a 64-bit destination while leaving the lower
32 bits unmodified.

https://github.com/llvm/llvm-project/pull/102885